@@ -422,6 +422,16 @@ static ulong zynq_clk_set_rate(struct clk *clk, ulong rate)
return -ENXIO;
}
}
+
+static int dummy_enable(struct clk *clk)
+{
+ /*
+ * Add implementation but by default all clocks are enabled
+ * after power up which is only one supported case now.
+ */
+ return 0;
+}
+
#else
static ulong zynq_clk_get_rate(struct clk *clk)
{
@@ -448,6 +458,7 @@ static struct clk_ops zynq_clk_ops = {
.get_rate = zynq_clk_get_rate,
#ifndef CONFIG_SPL_BUILD
.set_rate = zynq_clk_set_rate,
+ .enable = dummy_enable,
#endif
};
@@ -577,7 +577,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
debug("%s: CLK %ld\n", __func__, clock);
ret = clk_enable(&clk);
- if (ret && ret != -ENOSYS) {
+ if (ret) {
dev_err(dev, "failed to enable clock\n");
return ret;
}
@@ -477,13 +477,13 @@ static int zynq_gem_init(struct udevice *dev)
}
ret = clk_set_rate(&priv->clk, clk_rate);
- if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
+ if (IS_ERR_VALUE(ret)) {
dev_err(dev, "failed to set tx clock rate\n");
return ret;
}
ret = clk_enable(&priv->clk);
- if (ret && ret != -ENOSYS) {
+ if (ret) {
dev_err(dev, "failed to enable tx clock\n");
return ret;
}
@@ -127,7 +127,7 @@ static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
debug("%s: CLK %ld\n", __func__, clock);
ret = clk_enable(&clk);
- if (ret && ret != -ENOSYS) {
+ if (ret) {
dev_err(dev, "failed to enable clock\n");
return ret;
}
@@ -193,7 +193,7 @@ static int zynq_qspi_probe(struct udevice *bus)
}
ret = clk_enable(&clk);
- if (ret && ret != -ENOSYS) {
+ if (ret) {
dev_err(bus, "failed to enable clock\n");
return ret;
}
@@ -143,7 +143,7 @@ static int zynq_spi_probe(struct udevice *bus)
}
ret = clk_enable(&clk);
- if (ret && ret != -ENOSYS) {
+ if (ret) {
dev_err(bus, "failed to enable clock\n");
return ret;
}
@@ -373,7 +373,7 @@ static int zynqmp_qspi_probe(struct udevice *bus)
debug("%s: CLK %ld\n", __func__, clock);
ret = clk_enable(&clk);
- if (ret && ret != -ENOSYS) {
+ if (ret) {
dev_err(bus, "failed to enable clock\n");
return ret;
}
@@ -90,9 +90,8 @@ static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags)
/* Calculate timeout count */
count = timeout * clock_f;
- /* clk_enable will return -ENOSYS when it is not implemented */
ret = clk_enable(&wdt->clk);
- if (ret && ret != -ENOSYS) {
+ if (ret) {
dev_err(dev, "failed to enable clock\n");
return ret;
}
A lot of Xilinx drivers are checking -ENOSYS which means that clock driver doesn't have enable function. Remove this checking from drivers and create dummy enable function as was done for clk_fixed_rate driver by commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function"). Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- Changes in v2: - New patch is series drivers/clk/clk_zynq.c | 11 +++++++++++ drivers/mmc/zynq_sdhci.c | 2 +- drivers/net/zynq_gem.c | 4 ++-- drivers/serial/serial_zynq.c | 2 +- drivers/spi/zynq_qspi.c | 2 +- drivers/spi/zynq_spi.c | 2 +- drivers/spi/zynqmp_gqspi.c | 2 +- drivers/watchdog/xilinx_wwdt.c | 3 +-- 8 files changed, 19 insertions(+), 9 deletions(-)