| Message ID | ZR5vj5SgDa3RbDV5@swlinux02 |
|---|---|
| State | Accepted |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | [PULL] u-boot-riscv/master | expand |
On Thu, Oct 05, 2023 at 04:10:55PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 65b9b3462bec2966911658836983819ab4e4823e: > > Merge branch 'next_pinctrl_sync' of https://source.denx.de/u-boot/custodians/u-boot-sh (2023-10-02 15:19:02 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 7cfdacbe8020292845bd5eba63b576b8586c433c: > > configs: sifive: enable poweroff command on Unmatched (2023-10-04 18:23:59 +0800) > > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18005 > Applied to u-boot/master, thanks!
Hi Tom, The following changes since commit 65b9b3462bec2966911658836983819ab4e4823e: Merge branch 'next_pinctrl_sync' of https://source.denx.de/u-boot/custodians/u-boot-sh (2023-10-02 15:19:02 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 7cfdacbe8020292845bd5eba63b576b8586c433c: configs: sifive: enable poweroff command on Unmatched (2023-10-04 18:23:59 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18005 ---------------------------------------------------------------- + ae350: modify memory layout and target name + ae350: use generic RISC-V timer driver in S-mode + Support bootstage report for RISC-V + Support C extension exception command for RISC-V + Add Starfive timer support ---------------------------------------------------------------- Chanho Park (3): riscv: bootstage: correct bootstage_report guard riscv: timer: add timer_get_boot_us for BOOTSTAGE timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE Heinrich Schuchardt (4): cmd/exception: support RISC-V compressed instruction cmd/exception: test RISC-V 16 bit aligned instruction riscv: enable CONFIG_DEBUG_UART by default configs: sifive: enable poweroff command on Unmatched Kuan Lim Lee (1): timer: starfive: Add Starfive timer support Randolph (2): configs: andes: add vender prefix for target name configs: andes: rearrange SPL mode memory layout Yu Chien Peter Lin (1): riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode arch/riscv/Kconfig | 5 +- arch/riscv/cpu/andesv5/Kconfig | 3 +- arch/riscv/dts/Makefile | 2 +- arch/riscv/lib/bootm.c | 2 +- board/AndesTech/ae350/Kconfig | 2 +- cmd/riscv/exception.c | 34 +++++++++++-- configs/ae350_rv32_defconfig | 3 +- configs/ae350_rv32_spl_defconfig | 10 ++-- configs/ae350_rv32_spl_xip_defconfig | 7 +-- configs/ae350_rv32_xip_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- configs/ae350_rv64_spl_defconfig | 11 +++-- configs/ae350_rv64_spl_xip_defconfig | 8 +-- configs/ae350_rv64_xip_defconfig | 2 +- configs/sifive_unmatched_defconfig | 1 + drivers/timer/Kconfig | 16 +++++- drivers/timer/Makefile | 3 +- drivers/timer/riscv_aclint_timer.c | 23 +++++++++ drivers/timer/riscv_timer.c | 22 +++++++++ drivers/timer/starfive-timer.c | 94 ++++++++++++++++++++++++++++++++++++ 20 files changed, 223 insertions(+), 29 deletions(-) create mode 100644 drivers/timer/starfive-timer.c Best regards, Leo