| Message ID | ZL4v0q+lebVeB/mm@ubuntu01 |
|---|---|
| State | Accepted |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | [PULL] u-boot-riscv/master | expand |
On Mon, Jul 24, 2023 at 08:01:22AM +0000, Leo Liang wrote: > Hi Tom, > > The following changes since commit 247aa5a191159ea7e03bf1918e22fbbb784cd410: > > Merge branch '2023-07-21-assorted-TI-platform-updates' (2023-07-21 19:33:05 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to 6aabe229f8440c4960b904baf3aa33f692eea9a1: > > riscv: define a cache line size for the generic CPU (2023-07-24 13:22:24 +0800) > > CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17015 Applied to u-boot/master, thanks!
Hi Tom, The following changes since commit 247aa5a191159ea7e03bf1918e22fbbb784cd410: Merge branch '2023-07-21-assorted-TI-platform-updates' (2023-07-21 19:33:05 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 6aabe229f8440c4960b904baf3aa33f692eea9a1: riscv: define a cache line size for the generic CPU (2023-07-24 13:22:24 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17015 ---------------------------------------------------------------- - Set up per-hart stack before any function call - Sync visionfive2 board DTS with Linux - Define cache line size for USB 3.0 driver for RISC-V CPU ---------------------------------------------------------------- Bo Gan (1): riscv: setup per-hart stack earlier Chanho Park (2): configs: visionfive2: add a trailing space to prompt doc: visionfive2: apply a trailing space to the prompt Heinrich Schuchardt (1): riscv: define a cache line size for the generic CPU Xingyu Wu (5): clk: starfive: jh7110: Separate the PLL driver riscv: dts: jh7110: Add PLL clock controller node riscv: dts: jh7110: Add clock source from PLL dt-bindings: clock: jh7110: Modify clock id to be same with Linux clk: starfive: jh7110: Add of_xlate ops and macros for clock id conversion arch/riscv/cpu/generic/Kconfig | 1 + arch/riscv/cpu/start.S | 37 ++++++++++++++-------- arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 6 ++-- arch/riscv/dts/jh7110-u-boot.dtsi | 1 - arch/riscv/dts/jh7110.dtsi | 16 ++++++++-- configs/starfive_visionfive2_defconfig | 2 +- doc/board/starfive/visionfive2.rst | 18 +++++------ drivers/clk/starfive/clk-jh7110-pll.c | 103 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- drivers/clk/starfive/clk-jh7110.c | 306 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------------------------------------------------------------- drivers/clk/starfive/clk.h | 58 ++++++++------------------------- include/dt-bindings/clock/starfive,jh7110-crg.h | 101 +++++++++++++++++++++++++++++----------------------------- 11 files changed, 400 insertions(+), 249 deletions(-) Best regards, Leo