[PULL] u-boot-riscv/master

Hi Tom,

The following changes since commit ad320c237bea7ece659efaf6c1d43475e0e5db6a:

  Merge tag 'u-boot-stm32-20210906' of https://source.denx.de/u-boot/custodians/u-boot-stm (2021-09-06 10:31:56 -0400)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 30fa33dc808b8f28185bca9c812225cbc1ec6e8f:

  riscv: lib: modify the indent (2021-09-07 10:34:29 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9018

----------------------------------------------------------------
Heinrich Schuchardt (3):
      riscv: enable booting HiFive Unmatched from SATA
      configs: qemu-riscvXX_spl_defconfig enable CMD_SBI
      riscv: show code leading to exception

Thomas Skibo (1):
      riscv: Add missing sentinel in ocores_i2c.c

Zong Li (5):
      cache: add sifive composable cache driver
      common: board_r: support enable_caches for RISC-V
      riscv: lib: implement enable_caches for sifive cache
      board: sifive: use ccache driver instead of helper function
      riscv: lib: modify the indent

 arch/riscv/Kconfig                        |  5 +++
 arch/riscv/cpu/fu540/Kconfig              |  2 +
 arch/riscv/cpu/fu540/Makefile             |  1 -
 arch/riscv/cpu/fu540/cache.c              | 55 -----------------------
 arch/riscv/cpu/fu740/Kconfig              |  2 +
 arch/riscv/cpu/fu740/Makefile             |  1 -
 arch/riscv/cpu/fu740/cache.c              | 55 -----------------------
 arch/riscv/include/asm/arch-fu540/cache.h | 14 ------
 arch/riscv/include/asm/arch-fu740/cache.h | 14 ------
 arch/riscv/include/asm/cache.h            |  2 +-
 arch/riscv/lib/Makefile                   |  1 +
 arch/riscv/lib/cache.c                    |  4 ++
 arch/riscv/lib/interrupts.c               | 33 ++++++++++++++
 arch/riscv/lib/sifive_cache.c             | 27 +++++++++++
 board/sifive/unleashed/unleashed.c        | 10 +----
 board/sifive/unmatched/unmatched.c        | 11 ++---
 common/board_r.c                          |  4 +-
 configs/qemu-riscv32_spl_defconfig        |  1 +
 configs/qemu-riscv64_spl_defconfig        |  1 +
 configs/sifive_unmatched_defconfig        |  5 +++
 drivers/cache/Kconfig                     |  7 +++
 drivers/cache/Makefile                    |  1 +
 drivers/cache/cache-sifive-ccache.c       | 75 +++++++++++++++++++++++++++++++
 drivers/i2c/ocores_i2c.c                  |  1 +
 include/configs/sifive-unmatched.h        |  3 ++
 25 files changed, 176 insertions(+), 159 deletions(-)
 delete mode 100644 arch/riscv/cpu/fu540/cache.c
 delete mode 100644 arch/riscv/cpu/fu740/cache.c
 delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h
 delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h
 create mode 100644 arch/riscv/lib/sifive_cache.c
 create mode 100644 drivers/cache/cache-sifive-ccache.c

 Best regards,
 Leo

On Tue, Sep 07, 2021 at 04:20:50PM +0800, Leo Liang wrote:

> Hi Tom,
> 
> The following changes since commit ad320c237bea7ece659efaf6c1d43475e0e5db6a:
> 
>   Merge tag 'u-boot-stm32-20210906' of https://source.denx.de/u-boot/custodians/u-boot-stm (2021-09-06 10:31:56 -0400)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-riscv.git 
> 
> for you to fetch changes up to 30fa33dc808b8f28185bca9c812225cbc1ec6e8f:
> 
>   riscv: lib: modify the indent (2021-09-07 10:34:29 +0800)
> 
> CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9018
> 

Applied to u-boot/master, thanks!