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[v4,3/3] riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE

Message ID TY3P286MB2611A254F60EFF4AB178730F9812A@TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM
State Accepted
Delegated to: Andes
Headers show
Series arch: riscv: jh7110: Correctly zero L2 LIM | expand

Commit Message

Shengyu Qu Aug. 9, 2023, 1:11 p.m. UTC 
Add Kconfig item for Starfive JH7110 to select SPL_ZERO_MEM_BEFORE_USE.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
 arch/riscv/cpu/jh7110/Kconfig | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
index 4d9581165b..2e26d0731f 100644
--- a/arch/riscv/cpu/jh7110/Kconfig
+++ b/arch/riscv/cpu/jh7110/Kconfig
@@ -13,6 +13,7 @@  config STARFIVE_JH7110
 	select SUPPORT_SPL
 	select SPL_RAM if SPL
 	select SPL_STARFIVE_DDR
+	select SPL_ZERO_MEM_BEFORE_USE
 	select PINCTRL_STARFIVE_JH7110
 	imply MMC
 	imply MMC_BROKEN_CD