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Tue, 14 Jun 2016 02:18:07 -0700 Received: from XAP-PVEXMBX02.xlnx.xilinx.com ([fe80::6c95:7dae:8014:5ca1]) by XAP-PVEXCAS02.xlnx.xilinx.com ([::1]) with mapi id 14.03.0248.002; Tue, 14 Jun 2016 17:18:06 +0800 From: Siva Durga Prasad Paladugu To: "jagannadh.teki@gmail.com" , "Siva Durga Prasad Paladugu" , "u-boot@lists.denx.de" Thread-Topic: [PATCH v2 1/3] spi: spi_flash: Dont set quad enable for micron in all cases Thread-Index: AQHRtxwEHmMZGlik20W8pfzvEdyrVZ/ozJUQ Date: Tue, 14 Jun 2016 09:18:05 +0000 Message-ID: References: <1464245901-3983-1-git-send-email-sivadur@xilinx.com> In-Reply-To: <1464245901-3983-1-git-send-email-sivadur@xilinx.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.23.98.45] MIME-Version: 1.0 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22390.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.100; IPV:NLI; CTRY:US; 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X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(2401047)(5005006)(8121501046)(13024025)(13018025)(13017025)(13015025)(13023025)(3002001)(10201501046)(6055026); SRVR:BL2NAM02HT125; BCL:0; PCL:0; RULEID:; SRVR:BL2NAM02HT125; X-Forefront-PRVS: 09730BD177 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jun 2016 09:18:09.2700 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2NAM02HT125 Cc: Michal Simek Subject: Re: [U-Boot] [PATCH v2 1/3] spi: spi_flash: Dont set quad enable for micron in all cases X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" -----Original Message----- From: Siva Durga Prasad Paladugu [mailto:siva.durga.paladugu@xilinx.com] Sent: Thursday, May 26, 2016 12:28 PM To: u-boot@lists.denx.de Cc: Michal Simek ; jagannadh.teki@gmail.com; Siva Durga Prasad Paladugu Subject: [PATCH v2 1/3] spi: spi_flash: Dont set quad enable for micron in all cases Dont set quad enable for micron devices in all cases Setting the quad enable bit in micron expects all other commands like register reads on quad lines which may not be supported by some controllers. Hence, dont set the quad enable if controller driver sets the no_all_quad. Hi Jagan, Any comments on this series. If not, Please take this series. Regards, Siva Signed-off-by: Siva Durga Prasad Paladugu --- Changes for v2: - Newly added in series. --- drivers/mtd/spi/spi_flash.c | 13 ++++++++++++- include/spi.h | 2 +- 2 files changed, 13 insertions(+), 2 deletions(-) -- 1.7.1 diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 5451725..5b22ae2 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -926,6 +926,8 @@ static int micron_quad_enable(struct spi_flash *flash) static int set_quad_mode(struct spi_flash *flash, u8 idcode0) { + struct spi_slave *spi = flash->spi; + switch (idcode0) { #ifdef CONFIG_SPI_FLASH_MACRONIX case SPI_FLASH_CFI_MFR_MACRONIX: @@ -938,7 +940,16 @@ static int set_quad_mode(struct spi_flash *flash, u8 idcode0) #endif #ifdef CONFIG_SPI_FLASH_STMICRO case SPI_FLASH_CFI_MFR_STMICRO: - return micron_quad_enable(flash); + /* + * Set quad enable for micron only + * if controller supports sending of + * all commands on quad lines, otherwise + * dont enable it + */ + if (spi->no_all_quad) + return 0; + else + return micron_quad_enable(flash); #endif default: printf("SF: Need set QEB func for %02x flash\n", idcode0); diff --git a/include/spi.h b/include/spi.h index 4b88d39..17c6e4d 100644 --- a/include/spi.h +++ b/include/spi.h @@ -117,7 +117,7 @@ struct spi_slave { unsigned int max_write_size; void *memory_map; u8 option; - + u8 no_all_quad; u8 flags; #define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */ #define SPI_XFER_END BIT(1) /* Deassert CS after transfer */