From patchwork Tue Jan 20 23:38:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suriyan Ramasami X-Patchwork-Id: 431289 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id F2C81140276 for ; Wed, 21 Jan 2015 10:39:04 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D46824B616; Wed, 21 Jan 2015 00:39:02 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id grMFole95abU; Wed, 21 Jan 2015 00:39:02 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DF8154B600; Wed, 21 Jan 2015 00:39:01 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EB5FC4B600 for ; Wed, 21 Jan 2015 00:38:57 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gTGIEn3kLvf4 for ; Wed, 21 Jan 2015 00:38:57 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wi0-f179.google.com (mail-wi0-f179.google.com [209.85.212.179]) by theia.denx.de (Postfix) with ESMTPS id B50D44B5FA for ; Wed, 21 Jan 2015 00:38:54 +0100 (CET) Received: by mail-wi0-f179.google.com with SMTP id l15so18929992wiw.0 for ; Tue, 20 Jan 2015 15:38:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=orpf/GHzKtZlihxlfmzQd5z1L2/K08kYtT1berlXZRU=; b=h7CgZ1zpIeFpTzX8JNMYy/vadZnXl52VYICC36LhoBchRu1kqPezJ1+ZzQaPq9Z9AP OYE585USpI6R7jI/KcSMmen8jdDvhBb8oHQPRhZ+2c+LlVzZoyH0pqGA6+DRHReL94+U gwzThyzOhpROhbe9FHZqvq3s5Ot0Hno4w4tqILzuHbBbl2J+4o7GFOSWy13g8ddFaGXb d69suKD+wPndaWQkbGeh6F2QbiG1DAI/lAqHyR/gHto+fhuxdIlZxkBhigmatrhOlkdx vkqrBahZdCApuI5paHphdFpLvPR2f6JrSQ3D7rJyKUy5inw8OrUFYjq7/JVS7NrBrvqF Khtw== MIME-Version: 1.0 X-Received: by 10.180.95.9 with SMTP id dg9mr21636681wib.1.1421797134570; Tue, 20 Jan 2015 15:38:54 -0800 (PST) Received: by 10.217.69.131 with HTTP; Tue, 20 Jan 2015 15:38:54 -0800 (PST) In-Reply-To: References: <1421746560.6818.37.camel@collabora.co.uk> <1421772007.6818.42.camel@collabora.co.uk> <7hy4oxf8cv.fsf@deeprootsystems.com> <7hzj9ddqfd.fsf@deeprootsystems.com> Date: Tue, 20 Jan 2015 15:38:54 -0800 Message-ID: From: Suriyan Ramasami To: Kevin Hilman Cc: U-Boot Mailing List , Przemyslaw Marczak , Hyungwon Hwang Subject: Re: [U-Boot] Odroid XU3 - exynos5422 - SPL - iRAM/sRAM address X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Hello Kevin, On Tue, Jan 20, 2015 at 3:29 PM, Suriyan Ramasami wrote: > Hello Kevin, > > On Tue, Jan 20, 2015 at 2:43 PM, Kevin Hilman wrote: >> Suriyan Ramasami writes: >> >>> Hello Kevin, >>> These are the changes that would be necessary in uboot mainline for SPL: >>> >>> arch/arm/cpu/armv7/exynos/Kconfig >>> - select OF_CONTROL >>> + select SUPPORT_SPL >>> + select OF_CONTROL if !SPL_BUILD >>> >>> configs/odroid-xu3_defconfig >>> +CONFIG_SPL=y >>> >>> include/configs/odroid_xu3.h >>> #undef CONFIG_SPL_TEXT_BASE >>> #define CONFIG_SPL_TEXT_BASE 0x02027000 >>> >>> #undef CONFIG_SEC_FW_SIZE >>> #define CONFIG_SEC_FW_SIZE (15 << 10) /* 15 KB */ >> >> Thanks. With those changes, a build gives me: >> >> ./include/common.h:355:73: fatal error: asm/u-boot-sandbox.h: No such file or directory >> >> Sorry for the dumb questions, but I'm not very familiar with u-boot. >> I'm more comofortable in the kernel. >> > > The above used to work (a month ago). I shall check with current > mainline uboot and report back. > Sorry for the snafu. I t was my mistake. The correct diff for the configs is as below: >>> FWICT, mainline uboot does not have code to handle secure firmware. >>> For instance when secure firmware is present the address to poke a >>> jump address for the CPU is different (nsram +1c etc). This stems from >>> lowlevel_init.S being moved over to the NS area. This is also missing >>> in uboot mainline or so I think. >> >> Hmm, it seems the XU3 has secure firmware so I guess this wont' be useful >> for me yet? >> > > It should be relevant to you, as mainline uboot does not overlay the > NS area with a bootstrap code from lowlevel_init.S. At least I have > seen mainline linux src code using this address for waking up the CPUs > (so does XEN). > >> Curious what platforms you're testing this on? And are any of them >> using secure firmware? >> > > I am currently working only on the XU3 (I thought there was no > interest, so I let it slide). I probably should say that the Exynos > secure firmware support needs to be tweaked in U-Boot. Maybe other > SoCs are supported? I am not sure. > >> Also, I'm still a bit unsure where the switch from secure to NS world >> happens. Is that in BL1? or somewhere in BL2? If it's in BL2, have you >> tried switching secure mode off? >> > > I know for sure that the signed BL2 does switch from Hyp to NS. This > BL2 that I am referring to is HK's nomenclature, which translates to > BL1 (SPL) in UBoot lingo. Hence, this adds some confusion in the > discussions! > > The blobs are as follows: (possibly listed in the HK web pages) > BL0 (signed encrypted blob from Samsung). > This loads HK's signed BL2 (this is U-Boot SPL) > This loads U-Boot (U-Boot BL2) and the Trustzone > > Also, no matter what mode the odroid xu3 is in, the linux kernel from > what I can tell depending on the secure-firmware dts entry (which is > present) will use the NS + 1c area when powering on the CPU. Hence, > its mandatory to have code there. > > >>> I hope this helps you out. >> >> Well, it's certainly a step in the right direction, but not sure yet if >> I can use it on the odroid-xu3 as I'm still trying to understand the >> boot sequence. >> >> Kevin >> >>> The ddr init functions seem to be not correct for the 5422 (or so I >>> think). I do not have access to any of the Samsung docs, hence, one >>> solution was to copy over HKs ddr init function, and then the mainline >>> SPL runs. >>> >>> Regards >>> - Suriyan >>> >>> >>> On Tue, Jan 20, 2015 at 1:30 PM, Kevin Hilman wrote: >>>> Hello Suriyan, >>>> >>>> Suriyan Ramasami writes: >>>> >>>>> Hello Sjoerd Simons, >>>>> A signed BL2 which allows unsigned BL2 chain load is already >>>>> available for experimentation. Refer this link: >>>>> http://forum.odroid.com/viewtopic.php?f=98&t=6147#p58984 >>>>> The suriyan.bl2-hkxu3.1212.5422.zip blob contains a signed BL2 which >>>>> allows the same. >>>>> The layout of SD card is as follows: >>>>> >>>>> BL1 (1 to 30) 15K >>>>> BL2 (31 to 62) 16K >>>>> indicator block (63 to 64) 1K >>>>> uboot (65 to 2112) 1M >>>>> tzsw (2113 to 2624) 256K >>>>> unsigned BL2 (2625 to 2656) 16K >>>>> >>>>> A non zero in the first byte of the indicator block instructs the >>>>> signed BL2 to load the unsigned BL2 @ offset 2625. >>>> >>>> I'm currently running mainline u-boot, and hoping to test the series >>>> that powers down secondary cores on the odroid-xu3. That series applies >>>> and builds with mainline u-boot (v2015.01-rc3), but for it to work >>>> correctly, IIUC, I'll also need to build an SPL from mainline. >>>> >>>> Can you share your changes to mainline u-boot that enable the building >>>> of SPL? >>>> >>>> I'd like to try that using your BL2 that will load an unsigned BL2. >>>> >>>> Thanks, >>>> >>>> Kevin diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 7fcb5d2..39953e4 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -26,7 +26,8 @@ config TARGET_ODROID config TARGET_ODROID_XU3 bool "Exynos5422 Odroid board" - select OF_CONTROL + select SUPPORT_SPL + select OF_CONTROL if !SPL_BUILD config TARGET_ARNDALE bool "Exynos5250 Arndale board" diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index 74aa0cf..6000ec1 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -1,4 +1,5 @@ -CONFIG_ARM=y -CONFIG_ARCH_EXYNOS=y -CONFIG_TARGET_ODROID_XU3=y +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_EXYNOS=y ++S:CONFIG_TARGET_ODROID_XU3=y CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"