| Message ID | 94659b17f4acb8039b7f884d51a427f0f5f7684f.1662722729.git.weijie.gao@mediatek.com |
|---|---|
| State | Accepted |
| Commit | 7d928c3f2798fc2602e3c320b533fa721a92df38 |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | Add support for MediaTek MT7981/MT7986 SoCs - v3 | expand |
On Fri, Sep 9, 2022 at 2:59 PM Weijie Gao <weijie.gao@mediatek.com> wrote: > > This patch is a preparation for adding a new version of PDMA of which the > DMA descriptor fields has changed. Using bitfields will result in a complex > modification. Convert bitfields to u32 units can solve this problem easily. > > Reviewed-by: Simon Glass <sjg@chromium.org> > Tested-by: Daniel Golle <daniel@makrotopia.org> > Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> > --- > v3 changes: none > v2 changes: > Fix typo in commit message > --- > drivers/net/mtk_eth.c | 144 ++++++++++++++---------------------------- > drivers/net/mtk_eth.h | 32 ++++++++++ > 2 files changed, 80 insertions(+), 96 deletions(-) > > diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c > index ce4aa6e065..e3738b9277 100644 > --- a/drivers/net/mtk_eth.c > +++ b/drivers/net/mtk_eth.c > @@ -65,77 +65,6 @@ > (DP_DISCARD << MC_DP_S) | \ > (DP_DISCARD << UN_DP_S)) > > -struct pdma_rxd_info1 { > - u32 PDP0; > -}; > - > -struct pdma_rxd_info2 { > - u32 PLEN1 : 14; > - u32 LS1 : 1; > - u32 UN_USED : 1; > - u32 PLEN0 : 14; > - u32 LS0 : 1; > - u32 DDONE : 1; > -}; > - > -struct pdma_rxd_info3 { > - u32 PDP1; > -}; > - > -struct pdma_rxd_info4 { > - u32 FOE_ENTRY : 14; > - u32 CRSN : 5; > - u32 SP : 3; > - u32 L4F : 1; > - u32 L4VLD : 1; > - u32 TACK : 1; > - u32 IP4F : 1; > - u32 IP4 : 1; > - u32 IP6 : 1; > - u32 UN_USED : 4; > -}; > - > -struct pdma_rxdesc { > - struct pdma_rxd_info1 rxd_info1; > - struct pdma_rxd_info2 rxd_info2; > - struct pdma_rxd_info3 rxd_info3; > - struct pdma_rxd_info4 rxd_info4; > -}; > - > -struct pdma_txd_info1 { > - u32 SDP0; > -}; > - > -struct pdma_txd_info2 { > - u32 SDL1 : 14; > - u32 LS1 : 1; > - u32 BURST : 1; > - u32 SDL0 : 14; > - u32 LS0 : 1; > - u32 DDONE : 1; > -}; > - > -struct pdma_txd_info3 { > - u32 SDP1; > -}; > - > -struct pdma_txd_info4 { > - u32 VLAN_TAG : 16; > - u32 INS : 1; > - u32 RESV : 2; > - u32 UDF : 6; > - u32 FPORT : 3; > - u32 TSO : 1; > - u32 TUI_CO : 3; > -}; > - > -struct pdma_txdesc { > - struct pdma_txd_info1 txd_info1; > - struct pdma_txd_info2 txd_info2; > - struct pdma_txd_info3 txd_info3; > - struct pdma_txd_info4 txd_info4; > -}; > - > enum mtk_switch { > SW_NONE, > SW_MT7530, > @@ -151,13 +80,15 @@ enum mtk_switch { > struct mtk_soc_data { > u32 caps; > u32 ana_rgc3; > + u32 txd_size; > + u32 rxd_size; > }; > > struct mtk_eth_priv { > char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); > > - struct pdma_txdesc *tx_ring_noc; > - struct pdma_rxdesc *rx_ring_noc; > + void *tx_ring_noc; > + void *rx_ring_noc; > > int rx_dma_owner_idx0; > int tx_cpu_owner_idx0; > @@ -1202,14 +1133,16 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) > static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) > { > char *pkt_base = priv->pkt_pool; > + struct mtk_tx_dma *txd; > + struct mtk_rx_dma *rxd; > int i; > > mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0); > udelay(500); > > - memset(priv->tx_ring_noc, 0, NUM_TX_DESC * sizeof(struct pdma_txdesc)); > - memset(priv->rx_ring_noc, 0, NUM_RX_DESC * sizeof(struct pdma_rxdesc)); > - memset(priv->pkt_pool, 0, TOTAL_PKT_BUF_SIZE); > + memset(priv->tx_ring_noc, 0, NUM_TX_DESC * priv->soc->txd_size); > + memset(priv->rx_ring_noc, 0, NUM_RX_DESC * priv->soc->rxd_size); > + memset(priv->pkt_pool, 0xff, TOTAL_PKT_BUF_SIZE); > > flush_dcache_range((ulong)pkt_base, > (ulong)(pkt_base + TOTAL_PKT_BUF_SIZE)); > @@ -1218,17 +1151,21 @@ static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) > priv->tx_cpu_owner_idx0 = 0; > > for (i = 0; i < NUM_TX_DESC; i++) { > - priv->tx_ring_noc[i].txd_info2.LS0 = 1; > - priv->tx_ring_noc[i].txd_info2.DDONE = 1; > - priv->tx_ring_noc[i].txd_info4.FPORT = priv->gmac_id + 1; > + txd = priv->tx_ring_noc + i * priv->soc->txd_size; > + > + txd->txd1 = virt_to_phys(pkt_base); > + txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0; > + txd->txd4 = PDMA_TXD4_FPORT_SET(priv->gmac_id + 1); > > - priv->tx_ring_noc[i].txd_info1.SDP0 = virt_to_phys(pkt_base); > pkt_base += PKTSIZE_ALIGN; > } > > for (i = 0; i < NUM_RX_DESC; i++) { > - priv->rx_ring_noc[i].rxd_info2.PLEN0 = PKTSIZE_ALIGN; > - priv->rx_ring_noc[i].rxd_info1.PDP0 = virt_to_phys(pkt_base); > + rxd = priv->rx_ring_noc + i * priv->soc->rxd_size; > + > + rxd->rxd1 = virt_to_phys(pkt_base); > + rxd->rxd2 = PDMA_RXD2_PLEN0_SET(PKTSIZE_ALIGN); > + > pkt_base += PKTSIZE_ALIGN; > } > > @@ -1315,20 +1252,22 @@ static int mtk_eth_send(struct udevice *dev, void *packet, int length) > { > struct mtk_eth_priv *priv = dev_get_priv(dev); > u32 idx = priv->tx_cpu_owner_idx0; > + struct mtk_tx_dma *txd; > void *pkt_base; > > - if (!priv->tx_ring_noc[idx].txd_info2.DDONE) { > + txd = priv->tx_ring_noc + idx * priv->soc->txd_size; > + > + if (!(txd->txd2 & PDMA_TXD2_DDONE)) { > debug("mtk-eth: TX DMA descriptor ring is full\n"); > return -EPERM; > } > > - pkt_base = (void *)phys_to_virt(priv->tx_ring_noc[idx].txd_info1.SDP0); > + pkt_base = (void *)phys_to_virt(txd->txd1); > memcpy(pkt_base, packet, length); > flush_dcache_range((ulong)pkt_base, (ulong)pkt_base + > roundup(length, ARCH_DMA_MINALIGN)); > > - priv->tx_ring_noc[idx].txd_info2.SDL0 = length; > - priv->tx_ring_noc[idx].txd_info2.DDONE = 0; > + txd->txd2 = PDMA_TXD2_LS0 | PDMA_TXD2_SDL0_SET(length); > > priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC; > mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0); > @@ -1340,16 +1279,20 @@ static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp) > { > struct mtk_eth_priv *priv = dev_get_priv(dev); > u32 idx = priv->rx_dma_owner_idx0; > + struct mtk_rx_dma *rxd; > uchar *pkt_base; > u32 length; > > - if (!priv->rx_ring_noc[idx].rxd_info2.DDONE) { > + rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; > + > + if (!(rxd->rxd2 & PDMA_RXD2_DDONE)) { > debug("mtk-eth: RX DMA descriptor ring is empty\n"); > return -EAGAIN; > } > > - length = priv->rx_ring_noc[idx].rxd_info2.PLEN0; > - pkt_base = (void *)phys_to_virt(priv->rx_ring_noc[idx].rxd_info1.PDP0); > + length = PDMA_RXD2_PLEN0_GET(rxd->rxd2); > + > + pkt_base = (void *)phys_to_virt(rxd->rxd1); > invalidate_dcache_range((ulong)pkt_base, (ulong)pkt_base + > roundup(length, ARCH_DMA_MINALIGN)); > > @@ -1363,10 +1306,11 @@ static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length) > { > struct mtk_eth_priv *priv = dev_get_priv(dev); > u32 idx = priv->rx_dma_owner_idx0; > + struct mtk_rx_dma *rxd; > + > + rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; > > - priv->rx_ring_noc[idx].rxd_info2.DDONE = 0; > - priv->rx_ring_noc[idx].rxd_info2.LS0 = 0; > - priv->rx_ring_noc[idx].rxd_info2.PLEN0 = PKTSIZE_ALIGN; > + rxd->rxd2 = PDMA_RXD2_PLEN0_SET(PKTSIZE_ALIGN); > > mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx); > priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC; > @@ -1393,11 +1337,11 @@ static int mtk_eth_probe(struct udevice *dev) > return ret; > > /* Prepare for tx/rx rings */ > - priv->tx_ring_noc = (struct pdma_txdesc *) > - noncached_alloc(sizeof(struct pdma_txdesc) * NUM_TX_DESC, > + priv->tx_ring_noc = (void *) > + noncached_alloc(priv->soc->txd_size * NUM_TX_DESC, > ARCH_DMA_MINALIGN); > - priv->rx_ring_noc = (struct pdma_rxdesc *) > - noncached_alloc(sizeof(struct pdma_rxdesc) * NUM_RX_DESC, > + priv->rx_ring_noc = (void *) > + noncached_alloc(priv->soc->rxd_size * NUM_RX_DESC, > ARCH_DMA_MINALIGN); > > /* Set MAC mode */ > @@ -1554,18 +1498,26 @@ static int mtk_eth_of_to_plat(struct udevice *dev) > > static const struct mtk_soc_data mt7629_data = { > .ana_rgc3 = 0x128, > + .txd_size = sizeof(struct mtk_tx_dma), > + .rxd_size = sizeof(struct mtk_rx_dma), > }; > > static const struct mtk_soc_data mt7623_data = { > .caps = MT7623_CAPS, > + .txd_size = sizeof(struct mtk_tx_dma), > + .rxd_size = sizeof(struct mtk_rx_dma), > }; > > static const struct mtk_soc_data mt7622_data = { > .ana_rgc3 = 0x2028, > + .txd_size = sizeof(struct mtk_tx_dma), > + .rxd_size = sizeof(struct mtk_rx_dma), > }; > > static const struct mtk_soc_data mt7621_data = { > .caps = MT7621_CAPS, > + .txd_size = sizeof(struct mtk_tx_dma), > + .rxd_size = sizeof(struct mtk_rx_dma), > }; > > static const struct udevice_id mtk_eth_ids[] = { > diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h > index 15c2030617..65bc9fcc04 100644 > --- a/drivers/net/mtk_eth.h > +++ b/drivers/net/mtk_eth.h > @@ -10,6 +10,7 @@ > #define _MTK_ETH_H_ > > #include <linux/bitops.h> > +#include <linux/bitfield.h> > > enum mkt_eth_capabilities { > MTK_TRGMII_BIT, > @@ -435,4 +436,35 @@ enum mkt_eth_capabilities { > #define PHY_POWER_SAVING_M 0x300 > #define PHY_POWER_SAVING_TX 0x0 > > +/* PDMA descriptors */ > +struct mtk_rx_dma { > + unsigned int rxd1; > + unsigned int rxd2; > + unsigned int rxd3; > + unsigned int rxd4; > +} __packed __aligned(4); > + > +struct mtk_tx_dma { > + unsigned int txd1; > + unsigned int txd2; > + unsigned int txd3; > + unsigned int txd4; > +} __packed __aligned(4); > + > +/* PDMA TXD fields */ > +#define PDMA_TXD2_DDONE BIT(31) > +#define PDMA_TXD2_LS0 BIT(30) > +#define PDMA_TXD2_SDL0_M GENMASK(29, 16) > +#define PDMA_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_TXD2_SDL0_M, (_v)) > + > +#define PDMA_TXD4_FPORT_M GENMASK(27, 25) > +#define PDMA_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_TXD4_FPORT_M, (_v)) > + > +/* PDMA RXD fields */ > +#define PDMA_RXD2_DDONE BIT(31) > +#define PDMA_RXD2_LS0 BIT(30) > +#define PDMA_RXD2_PLEN0_M GENMASK(29, 16) > +#define PDMA_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_RXD2_PLEN0_M, (_v)) > +#define PDMA_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_RXD2_PLEN0_M, (_v)) > + > #endif /* _MTK_ETH_H_ */ > -- > 2.17.1 > Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index ce4aa6e065..e3738b9277 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -65,77 +65,6 @@ (DP_DISCARD << MC_DP_S) | \ (DP_DISCARD << UN_DP_S)) -struct pdma_rxd_info1 { - u32 PDP0; -}; - -struct pdma_rxd_info2 { - u32 PLEN1 : 14; - u32 LS1 : 1; - u32 UN_USED : 1; - u32 PLEN0 : 14; - u32 LS0 : 1; - u32 DDONE : 1; -}; - -struct pdma_rxd_info3 { - u32 PDP1; -}; - -struct pdma_rxd_info4 { - u32 FOE_ENTRY : 14; - u32 CRSN : 5; - u32 SP : 3; - u32 L4F : 1; - u32 L4VLD : 1; - u32 TACK : 1; - u32 IP4F : 1; - u32 IP4 : 1; - u32 IP6 : 1; - u32 UN_USED : 4; -}; - -struct pdma_rxdesc { - struct pdma_rxd_info1 rxd_info1; - struct pdma_rxd_info2 rxd_info2; - struct pdma_rxd_info3 rxd_info3; - struct pdma_rxd_info4 rxd_info4; -}; - -struct pdma_txd_info1 { - u32 SDP0; -}; - -struct pdma_txd_info2 { - u32 SDL1 : 14; - u32 LS1 : 1; - u32 BURST : 1; - u32 SDL0 : 14; - u32 LS0 : 1; - u32 DDONE : 1; -}; - -struct pdma_txd_info3 { - u32 SDP1; -}; - -struct pdma_txd_info4 { - u32 VLAN_TAG : 16; - u32 INS : 1; - u32 RESV : 2; - u32 UDF : 6; - u32 FPORT : 3; - u32 TSO : 1; - u32 TUI_CO : 3; -}; - -struct pdma_txdesc { - struct pdma_txd_info1 txd_info1; - struct pdma_txd_info2 txd_info2; - struct pdma_txd_info3 txd_info3; - struct pdma_txd_info4 txd_info4; -}; - enum mtk_switch { SW_NONE, SW_MT7530, @@ -151,13 +80,15 @@ enum mtk_switch { struct mtk_soc_data { u32 caps; u32 ana_rgc3; + u32 txd_size; + u32 rxd_size; }; struct mtk_eth_priv { char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); - struct pdma_txdesc *tx_ring_noc; - struct pdma_rxdesc *rx_ring_noc; + void *tx_ring_noc; + void *rx_ring_noc; int rx_dma_owner_idx0; int tx_cpu_owner_idx0; @@ -1202,14 +1133,16 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) { char *pkt_base = priv->pkt_pool; + struct mtk_tx_dma *txd; + struct mtk_rx_dma *rxd; int i; mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0); udelay(500); - memset(priv->tx_ring_noc, 0, NUM_TX_DESC * sizeof(struct pdma_txdesc)); - memset(priv->rx_ring_noc, 0, NUM_RX_DESC * sizeof(struct pdma_rxdesc)); - memset(priv->pkt_pool, 0, TOTAL_PKT_BUF_SIZE); + memset(priv->tx_ring_noc, 0, NUM_TX_DESC * priv->soc->txd_size); + memset(priv->rx_ring_noc, 0, NUM_RX_DESC * priv->soc->rxd_size); + memset(priv->pkt_pool, 0xff, TOTAL_PKT_BUF_SIZE); flush_dcache_range((ulong)pkt_base, (ulong)(pkt_base + TOTAL_PKT_BUF_SIZE)); @@ -1218,17 +1151,21 @@ static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) priv->tx_cpu_owner_idx0 = 0; for (i = 0; i < NUM_TX_DESC; i++) { - priv->tx_ring_noc[i].txd_info2.LS0 = 1; - priv->tx_ring_noc[i].txd_info2.DDONE = 1; - priv->tx_ring_noc[i].txd_info4.FPORT = priv->gmac_id + 1; + txd = priv->tx_ring_noc + i * priv->soc->txd_size; + + txd->txd1 = virt_to_phys(pkt_base); + txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0; + txd->txd4 = PDMA_TXD4_FPORT_SET(priv->gmac_id + 1); - priv->tx_ring_noc[i].txd_info1.SDP0 = virt_to_phys(pkt_base); pkt_base += PKTSIZE_ALIGN; } for (i = 0; i < NUM_RX_DESC; i++) { - priv->rx_ring_noc[i].rxd_info2.PLEN0 = PKTSIZE_ALIGN; - priv->rx_ring_noc[i].rxd_info1.PDP0 = virt_to_phys(pkt_base); + rxd = priv->rx_ring_noc + i * priv->soc->rxd_size; + + rxd->rxd1 = virt_to_phys(pkt_base); + rxd->rxd2 = PDMA_RXD2_PLEN0_SET(PKTSIZE_ALIGN); + pkt_base += PKTSIZE_ALIGN; } @@ -1315,20 +1252,22 @@ static int mtk_eth_send(struct udevice *dev, void *packet, int length) { struct mtk_eth_priv *priv = dev_get_priv(dev); u32 idx = priv->tx_cpu_owner_idx0; + struct mtk_tx_dma *txd; void *pkt_base; - if (!priv->tx_ring_noc[idx].txd_info2.DDONE) { + txd = priv->tx_ring_noc + idx * priv->soc->txd_size; + + if (!(txd->txd2 & PDMA_TXD2_DDONE)) { debug("mtk-eth: TX DMA descriptor ring is full\n"); return -EPERM; } - pkt_base = (void *)phys_to_virt(priv->tx_ring_noc[idx].txd_info1.SDP0); + pkt_base = (void *)phys_to_virt(txd->txd1); memcpy(pkt_base, packet, length); flush_dcache_range((ulong)pkt_base, (ulong)pkt_base + roundup(length, ARCH_DMA_MINALIGN)); - priv->tx_ring_noc[idx].txd_info2.SDL0 = length; - priv->tx_ring_noc[idx].txd_info2.DDONE = 0; + txd->txd2 = PDMA_TXD2_LS0 | PDMA_TXD2_SDL0_SET(length); priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC; mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0); @@ -1340,16 +1279,20 @@ static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp) { struct mtk_eth_priv *priv = dev_get_priv(dev); u32 idx = priv->rx_dma_owner_idx0; + struct mtk_rx_dma *rxd; uchar *pkt_base; u32 length; - if (!priv->rx_ring_noc[idx].rxd_info2.DDONE) { + rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; + + if (!(rxd->rxd2 & PDMA_RXD2_DDONE)) { debug("mtk-eth: RX DMA descriptor ring is empty\n"); return -EAGAIN; } - length = priv->rx_ring_noc[idx].rxd_info2.PLEN0; - pkt_base = (void *)phys_to_virt(priv->rx_ring_noc[idx].rxd_info1.PDP0); + length = PDMA_RXD2_PLEN0_GET(rxd->rxd2); + + pkt_base = (void *)phys_to_virt(rxd->rxd1); invalidate_dcache_range((ulong)pkt_base, (ulong)pkt_base + roundup(length, ARCH_DMA_MINALIGN)); @@ -1363,10 +1306,11 @@ static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length) { struct mtk_eth_priv *priv = dev_get_priv(dev); u32 idx = priv->rx_dma_owner_idx0; + struct mtk_rx_dma *rxd; + + rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; - priv->rx_ring_noc[idx].rxd_info2.DDONE = 0; - priv->rx_ring_noc[idx].rxd_info2.LS0 = 0; - priv->rx_ring_noc[idx].rxd_info2.PLEN0 = PKTSIZE_ALIGN; + rxd->rxd2 = PDMA_RXD2_PLEN0_SET(PKTSIZE_ALIGN); mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx); priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC; @@ -1393,11 +1337,11 @@ static int mtk_eth_probe(struct udevice *dev) return ret; /* Prepare for tx/rx rings */ - priv->tx_ring_noc = (struct pdma_txdesc *) - noncached_alloc(sizeof(struct pdma_txdesc) * NUM_TX_DESC, + priv->tx_ring_noc = (void *) + noncached_alloc(priv->soc->txd_size * NUM_TX_DESC, ARCH_DMA_MINALIGN); - priv->rx_ring_noc = (struct pdma_rxdesc *) - noncached_alloc(sizeof(struct pdma_rxdesc) * NUM_RX_DESC, + priv->rx_ring_noc = (void *) + noncached_alloc(priv->soc->rxd_size * NUM_RX_DESC, ARCH_DMA_MINALIGN); /* Set MAC mode */ @@ -1554,18 +1498,26 @@ static int mtk_eth_of_to_plat(struct udevice *dev) static const struct mtk_soc_data mt7629_data = { .ana_rgc3 = 0x128, + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), }; static const struct mtk_soc_data mt7623_data = { .caps = MT7623_CAPS, + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), }; static const struct mtk_soc_data mt7622_data = { .ana_rgc3 = 0x2028, + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), }; static const struct mtk_soc_data mt7621_data = { .caps = MT7621_CAPS, + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), }; static const struct udevice_id mtk_eth_ids[] = { diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h index 15c2030617..65bc9fcc04 100644 --- a/drivers/net/mtk_eth.h +++ b/drivers/net/mtk_eth.h @@ -10,6 +10,7 @@ #define _MTK_ETH_H_ #include <linux/bitops.h> +#include <linux/bitfield.h> enum mkt_eth_capabilities { MTK_TRGMII_BIT, @@ -435,4 +436,35 @@ enum mkt_eth_capabilities { #define PHY_POWER_SAVING_M 0x300 #define PHY_POWER_SAVING_TX 0x0 +/* PDMA descriptors */ +struct mtk_rx_dma { + unsigned int rxd1; + unsigned int rxd2; + unsigned int rxd3; + unsigned int rxd4; +} __packed __aligned(4); + +struct mtk_tx_dma { + unsigned int txd1; + unsigned int txd2; + unsigned int txd3; + unsigned int txd4; +} __packed __aligned(4); + +/* PDMA TXD fields */ +#define PDMA_TXD2_DDONE BIT(31) +#define PDMA_TXD2_LS0 BIT(30) +#define PDMA_TXD2_SDL0_M GENMASK(29, 16) +#define PDMA_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_TXD2_SDL0_M, (_v)) + +#define PDMA_TXD4_FPORT_M GENMASK(27, 25) +#define PDMA_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_TXD4_FPORT_M, (_v)) + +/* PDMA RXD fields */ +#define PDMA_RXD2_DDONE BIT(31) +#define PDMA_RXD2_LS0 BIT(30) +#define PDMA_RXD2_PLEN0_M GENMASK(29, 16) +#define PDMA_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_RXD2_PLEN0_M, (_v)) +#define PDMA_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_RXD2_PLEN0_M, (_v)) + #endif /* _MTK_ETH_H_ */