From patchwork Tue Aug 14 15:46:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Beno=C3=AEt_Th=C3=A9baudeau?= X-Patchwork-Id: 177347 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id EA4032C0098 for ; Wed, 15 Aug 2012 01:41:43 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 405232819B; Tue, 14 Aug 2012 17:41:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DOTZ7HaBO11f; Tue, 14 Aug 2012 17:41:41 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8240928188; Tue, 14 Aug 2012 17:41:38 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 21FC928188 for ; Tue, 14 Aug 2012 17:41:37 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WoqEZ4eltlpr for ; Tue, 14 Aug 2012 17:41:36 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from zose-mta15.web4all.fr (zose-mta15.web4all.fr [176.31.217.11]) by theia.denx.de (Postfix) with ESMTP id 35D5828187 for ; Tue, 14 Aug 2012 17:41:34 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by zose-mta15.web4all.fr (Postfix) with ESMTP id 917722D2CB; Tue, 14 Aug 2012 17:44:15 +0200 (CEST) X-Virus-Scanned: amavisd-new at zose1.web4all.fr Received: from zose-mta15.web4all.fr ([127.0.0.1]) by localhost (zose-mta15.web4all.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BjSVD6j9f7vv; Tue, 14 Aug 2012 17:44:15 +0200 (CEST) Received: from zose-store12.web4all.fr (zose-store-12.w4a.fr [178.33.204.48]) by zose-mta15.web4all.fr (Postfix) with ESMTP id 025D32C373; Tue, 14 Aug 2012 17:44:15 +0200 (CEST) Date: Tue, 14 Aug 2012 17:46:54 +0200 (CEST) From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= To: U-Boot-Users ML Message-ID: <883852451.2404814.1344959214390.JavaMail.root@advansee.com> MIME-Version: 1.0 X-Originating-IP: [88.188.188.98] X-Mailer: Zimbra 7.2.0_GA_2669 (ZimbraWebClient - FF3.0 (Win)/7.2.0_GA_2669) Subject: [U-Boot] [PATCH 1/2] mx5: Add default pin initializers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Create default pin initialization functions for the default iomux function assignments of the main peripherals. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic --- .../arch/arm/cpu/armv7/mx5/soc.c | 139 ++++++++++++++++++++ .../arch/arm/include/asm/arch-mx5/sys_proto.h | 5 + 2 files changed, 144 insertions(+) diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/soc.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/soc.c index 3f5a4f7..ee19b54 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/soc.c +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/soc.c @@ -25,6 +25,8 @@ #include #include +#include +#include #include #include @@ -71,6 +73,143 @@ u32 get_cpu_rev(void) return system_rev; } +#ifdef CONFIG_MXC_UART +#if CONFIG_MXC_UART_BASE == UART1_BASE +#ifdef CONFIG_MX51 +void mx51_uart1_init_pins(void) +{ + int in_pad, out_pad; + + /* Set up pins for UART1. */ + mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); + + mxc_iomux_set_input(MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_input(MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT, + INPUT_CTL_PATH0); + + in_pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW; + out_pad = PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH | + PAD_CTL_SRE_SLOW; + + mxc_iomux_set_pad(MX51_PIN_UART1_RXD, in_pad); + mxc_iomux_set_pad(MX51_PIN_UART1_TXD, out_pad); + mxc_iomux_set_pad(MX51_PIN_UART1_RTS, in_pad); + mxc_iomux_set_pad(MX51_PIN_UART1_CTS, out_pad); +} +#endif +#endif +#endif + +#ifdef CONFIG_MXC_SPI +void mx51_ecspi1_init_pins(void) +{ + int act_lo_pad, act_hi_pad; + + /* Set up pins for eCSPI1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT0); + + act_lo_pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH | + PAD_CTL_SRE_SLOW; + act_hi_pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PD | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH | + PAD_CTL_SRE_SLOW; + + mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, act_hi_pad); + mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, act_lo_pad); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, act_hi_pad); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, act_hi_pad); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, act_lo_pad); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, act_lo_pad); +} +#endif + +#ifdef CONFIG_FSL_ESDHC +void mx51_esdhc1_init_pins(void) +{ + int out_pad, io_pad; + + /* Set up pins for eSDHC1. */ + mxc_request_iomux(MX51_PIN_SD1_CMD, + IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD1_DATA0, + IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD1_DATA1, + IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD1_DATA2, + IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD1_DATA3, + IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_GPIO1_1, + IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0); /* WP */ + mxc_request_iomux(MX51_PIN_GPIO1_0, + IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0); /* CD */ + + out_pad = PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_47K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST; + io_pad = PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_47K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST; + + mxc_iomux_set_pad(MX51_PIN_SD1_CMD, io_pad); + mxc_iomux_set_pad(MX51_PIN_SD1_CLK, out_pad); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, io_pad); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, io_pad); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, io_pad); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, io_pad); + mxc_iomux_set_pad(MX51_PIN_GPIO1_1, PAD_CTL_HYS_ENABLE); /* WP */ + mxc_iomux_set_pad(MX51_PIN_GPIO1_0, PAD_CTL_HYS_ENABLE); /* CD */ +} + +void mx51_esdhc2_init_pins(void) +{ + int out_pad, io_pad; + + /* Set up pins for eSDHC2. */ + mxc_request_iomux(MX51_PIN_SD2_CMD, + IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD2_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD2_DATA0, + IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD2_DATA1, + IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD2_DATA2, + IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD2_DATA3, + IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0); + + out_pad = PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_47K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST; + io_pad = PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_47K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST; + + mxc_iomux_set_pad(MX51_PIN_SD2_CMD, io_pad); + mxc_iomux_set_pad(MX51_PIN_SD2_CLK, out_pad); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, io_pad); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, io_pad); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, io_pad); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, io_pad); +} +#endif + #if defined(CONFIG_FEC_MXC) void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/sys_proto.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/sys_proto.h index 7b5246e..ce4a94c 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/sys_proto.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -39,4 +39,9 @@ u32 get_ahb_clk(void); u32 get_periph_clk(void); char *get_reset_cause(void); +void mx51_uart1_init_pins(void); +void mx51_ecspi1_init_pins(void); +void mx51_esdhc1_init_pins(void); +void mx51_esdhc2_init_pins(void); + #endif