From patchwork Tue Aug 14 14:44:33 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Beno=C3=AEt_Th=C3=A9baudeau?= X-Patchwork-Id: 177296 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5629C2C0096 for ; Wed, 15 Aug 2012 00:39:21 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0A46E280B6; Tue, 14 Aug 2012 16:39:20 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id otePvlbPTJYF; Tue, 14 Aug 2012 16:39:19 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6E475280A0; Tue, 14 Aug 2012 16:39:18 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8A514280A0 for ; Tue, 14 Aug 2012 16:39:16 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BYxNTlrL75e1 for ; Tue, 14 Aug 2012 16:39:16 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from zose-mta11.web4all.fr (zose-mta-11.w4a.fr [178.33.204.86]) by theia.denx.de (Postfix) with ESMTP id 646A2280B1 for ; Tue, 14 Aug 2012 16:39:13 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by zose-mta11.web4all.fr (Postfix) with ESMTP id 15EBC46059; Tue, 14 Aug 2012 16:44:00 +0200 (CEST) X-Virus-Scanned: amavisd-new at zose1.web4all.fr Received: from zose-mta11.web4all.fr ([127.0.0.1]) by localhost (zose-mta11.web4all.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RX-J9OSveFH2; Tue, 14 Aug 2012 16:43:59 +0200 (CEST) Received: from zose-store12.web4all.fr (zose-store12.web4all.fr [178.33.204.49]) by zose-mta11.web4all.fr (Postfix) with ESMTP id 91A184602F; Tue, 14 Aug 2012 16:43:59 +0200 (CEST) Date: Tue, 14 Aug 2012 16:44:33 +0200 (CEST) From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= To: U-Boot-Users ML Message-ID: <633607689.2402754.1344955473539.JavaMail.root@advansee.com> In-Reply-To: <1488400768.2402688.1344955435673.JavaMail.root@advansee.com> MIME-Version: 1.0 X-Originating-IP: [88.188.188.98] X-Mailer: Zimbra 7.2.0_GA_2669 (ZimbraWebClient - FF3.0 (Win)/7.2.0_GA_2669) Subject: [U-Boot] [PATCH 4/4] mx5: Mark lowlevel_init board-specific code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The mx5 lowlevel_init.S contains board-specific code based on the reference design. Let's keep it since it avoids creating new lowlevel_init files and it may be used by many boards. But add a config to make it optional in order not to cause issues on boards not following this part of the reference design. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic --- .../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 2 +- .../doc/README.imx5 | 5 +++++ .../include/configs/efikamx.h | 1 + .../include/configs/mx51evk.h | 1 + .../include/configs/vision2.h | 1 + 5 files changed, 9 insertions(+), 1 deletion(-) diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index d0f75fa..b25b3a7 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -330,7 +330,7 @@ ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */ -#if defined(CONFIG_MX51) +#if defined(CONFIG_SYS_MAIN_PWR_ON) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] orr r1, r1, #1 << 23 diff --git u-boot-4d3c95f.orig/doc/README.imx5 u-boot-4d3c95f/doc/README.imx5 index 938d3da..85d476f 100644 --- u-boot-4d3c95f.orig/doc/README.imx5 +++ u-boot-4d3c95f/doc/README.imx5 @@ -20,3 +20,8 @@ i.MX5x SoCs. mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. + +1.3 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup. + This option should be enabled for boards having a SYS_ON_OFF_CTL signal + connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the + reference designs. diff --git u-boot-4d3c95f.orig/include/configs/efikamx.h u-boot-4d3c95f/include/configs/efikamx.h index 143b0f0..792b51b 100644 --- u-boot-4d3c95f.orig/include/configs/efikamx.h +++ u-boot-4d3c95f/include/configs/efikamx.h @@ -270,5 +270,6 @@ #define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35145 +#define CONFIG_SYS_MAIN_PWR_ON #endif diff --git u-boot-4d3c95f.orig/include/configs/mx51evk.h u-boot-4d3c95f/include/configs/mx51evk.h index e975f54..6867f7b 100644 --- u-boot-4d3c95f.orig/include/configs/mx51evk.h +++ u-boot-4d3c95f/include/configs/mx51evk.h @@ -242,6 +242,7 @@ #define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 +#define CONFIG_SYS_MAIN_PWR_ON /*----------------------------------------------------------------------- * FLASH and environment organization diff --git u-boot-4d3c95f.orig/include/configs/vision2.h u-boot-4d3c95f/include/configs/vision2.h index ed004a6..3ce4906 100644 --- u-boot-4d3c95f.orig/include/configs/vision2.h +++ u-boot-4d3c95f/include/configs/vision2.h @@ -203,6 +203,7 @@ /* 166 MHz DDR RAM */ #define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_CLKTL_CBCDR 0x19239100 +#define CONFIG_SYS_MAIN_PWR_ON #define CONFIG_SYS_NO_FLASH