diff --git a/arch/arm/dts/mt7988-u-boot.dtsi b/arch/arm/dts/mt7988-u-boot.dtsi
new file mode 100644
index 0000000000..43e00a36ef
--- /dev/null
+++ b/arch/arm/dts/mt7988-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+&system_clk {
+	bootph-all;
+};
+
+&spi_clk {
+	bootph-all;
+};
+
+&uart0 {
+	bootph-all;
+};
+
+&uart1 {
+	bootph-all;
+};
+
+&uart2 {
+	bootph-all;
+};
diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
new file mode 100644
index 0000000000..ddd629e8c9
--- /dev/null
+++ b/arch/arm/dts/mt7988.dtsi
@@ -0,0 +1,391 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt7988-clk.h>
+#include <dt-bindings/reset/mt7988-reset.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "mediatek,mt7988-rfb";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x0>;
+			mediatek,hwver = <&hwver>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x1>;
+			mediatek,hwver = <&hwver>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x2>;
+			mediatek,hwver = <&hwver>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x3>;
+			mediatek,hwver = <&hwver>;
+		};
+	};
+
+	system_clk: dummy40m {
+		compatible = "fixed-clock";
+		clock-frequency = <40000000>;
+		#clock-cells = <0>;
+	};
+
+	spi_clk: dummy208m {
+		compatible = "fixed-clock";
+		clock-frequency = <208000000>;
+		#clock-cells = <0>;
+	};
+
+	hwver: hwver {
+		compatible = "mediatek,hwver", "syscon";
+		reg = <0 0x8000000 0 0x1000>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		clock-frequency = <13000000>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	watchdog: watchdog@1001c000 {
+		compatible = "mediatek,mt7622-wdt",
+			     "mediatek,mt6589-wdt",
+			     "syscon";
+		reg = <0 0x1001c000 0 0x1000>;
+		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+		#reset-cells = <1>;
+	};
+
+	gic: interrupt-controller@c000000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+		interrupt-controller;
+		reg = <0 0x0c000000 0 0x40000>,  /* GICD */
+		      <0 0x0c080000 0 0x200000>; /* GICR */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	infracfg_ao_cgs: infracfg_ao_cgs@10001000 {
+		compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon";
+		reg = <0 0x10001000 0 0x1000>;
+		clock-parent = <&infracfg_ao>;
+		#clock-cells = <1>;
+	};
+
+	apmixedsys: apmixedsys@1001e000 {
+		compatible = "mediatek,mt7988-fixed-plls", "syscon";
+		reg = <0 0x1001e000 0 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	topckgen: topckgen@1001b000 {
+		compatible = "mediatek,mt7988-topckgen", "syscon";
+		reg = <0 0x1001b000 0 0x1000>;
+		clock-parent = <&apmixedsys>;
+		#clock-cells = <1>;
+	};
+
+	pinctrl: pinctrl@1001f000 {
+		compatible = "mediatek,mt7988-pinctrl";
+		reg = <0 0x1001f000 0 0x1000>,
+		      <0 0x11c10000 0 0x1000>,
+		      <0 0x11d00000 0 0x1000>,
+		      <0 0x11d20000 0 0x1000>,
+		      <0 0x11e00000 0 0x1000>,
+		      <0 0x11f00000 0 0x1000>,
+		      <0 0x1000b000 0 0x1000>;
+		reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base",
+			    "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
+			    "eint";
+		gpio: gpio-controller {
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
+
+	sgmiisys0: syscon@10060000 {
+		compatible = "mediatek,mt7988-sgmiisys_0", "syscon";
+		reg = <0 0x10060000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	sgmiisys1: syscon@10070000 {
+		compatible = "mediatek,mt7988-sgmiisys_1", "syscon";
+		reg = <0 0x10070000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	usxgmiisys0: syscon@10080000 {
+		compatible = "mediatek,mt7988-usxgmiisys_0", "syscon";
+		reg = <0 0x10080000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	usxgmiisys1: syscon@10081000 {
+		compatible = "mediatek,mt7988-usxgmiisys_1", "syscon";
+		reg = <0 0x10081000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	xfi_pextp0: syscon@11f20000 {
+		compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
+		reg = <0 0x11f20000 0 0x10000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	xfi_pextp1: syscon@11f30000 {
+		compatible = "mediatek,mt7988-xfi_pextp_1", "syscon";
+		reg = <0 0x11f30000 0 0x10000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	xfi_pll: syscon@11f40000 {
+		compatible = "mediatek,mt7988-xfi_pll", "syscon";
+		reg = <0 0x11f40000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	topmisc: topmisc@11d10000 {
+		compatible = "mediatek,mt7988-topmisc", "syscon",
+			     "mediatek,mt7988-power-controller";
+		reg = <0 0x11d10000 0 0x10000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	infracfg_ao: infracfg@10001000 {
+		compatible = "mediatek,mt7988-infracfg", "syscon";
+		reg = <0 0x10001000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+	};
+
+	uart0: serial@11000000 {
+		compatible = "mediatek,hsuart";
+		reg = <0 0x11000000 0 0x100>;
+		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+				  <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+					 <&infracfg_ao CK_INFRA_UART_O0>;
+		status = "disabled";
+	};
+
+	uart1: serial@11000100 {
+		compatible = "mediatek,hsuart";
+		reg = <0 0x11000100 0 0x100>;
+		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+				  <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+					 <&infracfg_ao CK_INFRA_UART_O1>;
+		status = "disabled";
+	};
+
+	uart2: serial@11000200 {
+		compatible = "mediatek,hsuart";
+		reg = <0 0x11000200 0 0x100>;
+		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
+		assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+				  <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+					 <&infracfg_ao CK_INFRA_UART_O2>;
+		status = "disabled";
+	};
+
+	i2c0: i2c@11003000 {
+		compatible = "mediatek,mt7988-i2c",
+			     "mediatek,mt7981-i2c";
+		reg = <0 0x11003000 0 0x1000>,
+		      <0 0x10217080 0 0x80>;
+		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+		clock-div = <1>;
+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+		clock-names = "main", "dma";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@11004000 {
+		compatible = "mediatek,mt7988-i2c",
+			     "mediatek,mt7981-i2c";
+		reg = <0 0x11004000 0 0x1000>,
+		      <0 0x10217100 0 0x80>;
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+		clock-div = <1>;
+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+		clock-names = "main", "dma";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@11005000 {
+		compatible = "mediatek,mt7988-i2c",
+			     "mediatek,mt7981-i2c";
+		reg = <0 0x11005000 0 0x1000>,
+		      <0 0x10217180 0 0x80>;
+		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+		clock-div = <1>;
+		clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
+			 <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+		clock-names = "main", "dma";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	pwm: pwm@10048000 {
+		compatible = "mediatek,mt7988-pwm";
+		reg = <0 0x10048000 0 0x1000>;
+		#pwm-cells = <2>;
+		clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
+			 <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
+		clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
+			      "pwm4","pwm5","pwm6","pwm7","pwm8";
+		status = "disabled";
+	};
+
+	snand: snand@11001000 {
+		compatible = "mediatek,mt7988-snand",
+			     "mediatek,mt7986-snand";
+		reg = <0 0x11001000 0 0x1000>,
+		      <0 0x11002000 0 0x1000>;
+		reg-names = "nfi", "ecc";
+		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&infracfg_ao CK_INFRA_SPINFI>,
+			 <&infracfg_ao CK_INFRA_NFI>,
+			 <&infracfg_ao CK_INFRA_66M_NFI_HCK>;
+		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
+		assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
+				  <&topckgen CK_TOP_NFI1X_SEL>;
+		assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
+					 <&topckgen CK_TOP_CB_M_D8>;
+		status = "disabled";
+	};
+
+	spi0: spi@1100a000 {
+		compatible = "mediatek,ipm-spi";
+		reg = <0 0x11007000 0 0x100>;
+		clocks = <&spi_clk>,
+			 <&spi_clk>;
+		clock-names = "sel-clk", "spi-clk";
+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	spi1: spi@1100b000 {
+		compatible = "mediatek,ipm-spi";
+		reg = <0 0x11008000 0 0x100>;
+		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	spi2: spi@11009000 {
+		compatible = "mediatek,ipm-spi";
+		reg = <0 0x11009000 0 0x100>;
+		clocks = <&spi_clk>,
+			 <&spi_clk>;
+		clock-names = "sel-clk", "spi-clk";
+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	mmc0: mmc@11230000 {
+		compatible = "mediatek,mt7988-mmc",
+			     "mediatek,mt7986-mmc";
+		reg = <0 0x11230000 0 0x1000>;
+		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>,
+			 <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>,
+			 <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>,
+			 <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>;
+		clock-names = "source", "hclk", "source_cg", "axi_cg";
+		status = "disabled";
+	};
+
+	ethdma: syscon@15000000 {
+		compatible = "mediatek,mt7988-ethdma", "syscon";
+		reg = <0 0x15000000 0 0x20000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	ethwarp: syscon@15031000 {
+		compatible = "mediatek,mt7988-ethwarp", "syscon";
+		reg = <0 0x15031000 0 0x1000>;
+		clock-parent = <&topckgen>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	eth: ethernet@15100000 {
+		compatible = "mediatek,mt7988-eth", "syscon";
+		reg = <0 0x15100000 0 0x20000>;
+		mediatek,ethsys = <&ethdma>;
+		mediatek,sgmiisys = <&sgmiisys0>;
+		mediatek,usxgmiisys = <&usxgmiisys0>;
+		mediatek,xfi_pextp = <&xfi_pextp0>;
+		mediatek,xfi_pll = <&xfi_pll>;
+		mediatek,infracfg = <&topmisc>;
+		mediatek,toprgu = <&watchdog>;
+		resets = <&ethdma ETHDMA_FE_RST>, <&ethwarp ETHWARP_GSW_RST>;
+		reset-names = "fe", "mcm";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		mediatek,mcm;
+		status = "disabled";
+	};
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 04aa2fd97f..8971e2d2b0 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -58,6 +58,15 @@ config TARGET_MT7986
 	  including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
 	  Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe.
 
+config TARGET_MT7988
+	bool "MediaTek MT7988 SoC"
+	select ARM64
+	select CPU
+	help
+	  The MediaTek MT7988 is a ARM64-based SoC with a quad-core Cortex-A73.
+	  including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
+	  10 Gigabit Ethernet , I2C, and PCIe.
+
 config TARGET_MT8183
 	bool "MediaTek MT8183 SoC"
 	select ARM64
@@ -104,6 +113,7 @@ config SYS_BOARD
 	default "mt7629" if TARGET_MT7629
 	default "mt7981" if TARGET_MT7981
 	default "mt7986" if TARGET_MT7986
+	default "mt7988" if TARGET_MT7988
 	default "mt8183" if TARGET_MT8183
 	default "mt8512" if TARGET_MT8512
 	default "mt8516" if TARGET_MT8516
@@ -121,6 +131,7 @@ config SYS_CONFIG_NAME
 	default "mt7629" if TARGET_MT7629
 	default "mt7981" if TARGET_MT7981
 	default "mt7986" if TARGET_MT7986
+	default "mt7988" if TARGET_MT7988
 	default "mt8183" if TARGET_MT8183
 	default "mt8512" if TARGET_MT8512
 	default "mt8516" if TARGET_MT8516
@@ -135,7 +146,7 @@ config MTK_BROM_HEADER_INFO
 	string
 	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
 	default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
-	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
+	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988
 	default "lk=1" if TARGET_MT7623
 
 endif
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index fc85293f71..71aa341e34 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_TARGET_MT7623) += mt7623/
 obj-$(CONFIG_TARGET_MT7629) += mt7629/
 obj-$(CONFIG_TARGET_MT7981) += mt7981/
 obj-$(CONFIG_TARGET_MT7986) += mt7986/
+obj-$(CONFIG_TARGET_MT7988) += mt7988/
 obj-$(CONFIG_TARGET_MT8183) += mt8183/
 obj-$(CONFIG_TARGET_MT8516) += mt8516/
 obj-$(CONFIG_TARGET_MT8518) += mt8518/
diff --git a/arch/arm/mach-mediatek/mt7988/Makefile b/arch/arm/mach-mediatek/mt7988/Makefile
new file mode 100644
index 0000000000..007eb4a367
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7988/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
diff --git a/arch/arm/mach-mediatek/mt7988/init.c b/arch/arm/mach-mediatek/mt7988/init.c
new file mode 100644
index 0000000000..082f12bf65
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7988/init.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+#include <asm/u-boot.h>
+#include <asm/system.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SZ_8G				_AC(0x200000000, ULL)
+
+int dram_init(void)
+{
+	int ret;
+
+	ret = fdtdec_setup_mem_size_base();
+	if (ret)
+		return ret;
+
+	gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_8G);
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = gd->ram_base;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	psci_system_reset();
+}
+
+static struct mm_region mt7988_mem_map[] = {
+	{
+		/* DDR */
+		.virt = 0x40000000UL,
+		.phys = 0x40000000UL,
+		.size = 0x200000000ULL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+	}, {
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 0x40000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		0,
+	}
+};
+
+struct mm_region *mem_map = mt7988_mem_map;
diff --git a/arch/arm/mach-mediatek/mt7988/lowlevel_init.S b/arch/arm/mach-mediatek/mt7988/lowlevel_init.S
new file mode 100644
index 0000000000..2ae3cc4848
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7988/lowlevel_init.S
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/*
+ * Switch from AArch64 EL2 to AArch32 EL2
+ * @param inputs:
+ * x0: argument, zero
+ * x1: machine nr
+ * x2: fdt address
+ * x3: input argument
+ * x4: kernel entry point
+ * @param outputs for secure firmware:
+ * x0: function id
+ * x1: kernel entry point
+ * x2: machine nr
+ * x3: fdt address
+*/
+
+.global armv8_el2_to_aarch32
+armv8_el2_to_aarch32:
+	mov     x3, x2
+	mov     x2, x1
+	mov     x1, x4
+	mov	x4, #0
+	ldr x0, =0x82000200
+	SMC #0
+	ret
