diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 724b5d2..b513918 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier:    GPL-2.0+
 #
 
-#dtb-$(CONFIG_XXX) += xxx.dtb
+dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
new file mode 100644
index 0000000..99e7f64
--- /dev/null
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2015 Purna Chandra Mandal, purna.mandal@microchip.com
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "pic32mzda.dtsi"
+
+/ {
+    model = "Microchip PIC32MZDASK";
+    compatible = "microchip,pic32mzdask", "microchip,pic32mzda";
+
+    aliases {
+        console = &uart2;
+        serial0 = &uart2;
+    };
+
+    chosen {
+        stdout-path = "serial0:115200n8";
+    };
+};
+
+&clock {
+    status = "okay";
+    u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+    status = "okay";
+    u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+    status = "okay";
+    u-boot,dm-pre-reloc;
+};
diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
index 9983131..f82df37 100644
--- a/arch/mips/mach-pic32/Kconfig
+++ b/arch/mips/mach-pic32/Kconfig
@@ -24,6 +24,12 @@ endchoice
 choice
     prompt "Board select"
 
+config TARGET_PIC32MZDASK
+    bool "Microchip PIC32MZ[DA] Starter Kit"
+    depends on SOC_PIC32MZDA
+    help
+      This supports Microchip PIC32MZ[DA] Starter Kit.
+
 endchoice
 
 config PIC32_SUPPORTS_FDT_BOOT
@@ -31,4 +37,5 @@ config PIC32_SUPPORTS_FDT_BOOT
     select MIPS_BOOT_FDT
     select MIPS_BOOT_CMDLINE_LEGACY
 
+source "board/microchip/pic32mzda/Kconfig"
 endmenu
diff --git a/board/microchip/pic32mzda/Kconfig b/board/microchip/pic32mzda/Kconfig
new file mode 100644
index 0000000..8acb393
--- /dev/null
+++ b/board/microchip/pic32mzda/Kconfig
@@ -0,0 +1,13 @@
+
+if TARGET_PIC32MZDASK
+
+config SYS_BOARD
+    default "pic32mzda"
+
+config SYS_VENDOR
+    default "microchip"
+
+config SYS_CONFIG_NAME
+    default "pic32mzdask"
+
+endif
diff --git a/board/microchip/pic32mzda/MAINTAINERS b/board/microchip/pic32mzda/MAINTAINERS
new file mode 100644
index 0000000..c934f1a
--- /dev/null
+++ b/board/microchip/pic32mzda/MAINTAINERS
@@ -0,0 +1,6 @@
+PIC32MZDASK BOARD
+M:    Purna Chandra Mandal <purna.mandal@microchip.com>
+S:    Maintained
+F:    board/microchip/pic32mzda/
+F:    include/configs/pic32mzdask.h
+F:    configs/pic32mzdask_defconfig
diff --git a/board/microchip/pic32mzda/Makefile b/board/microchip/pic32mzda/Makefile
new file mode 100644
index 0000000..93733b4
--- /dev/null
+++ b/board/microchip/pic32mzda/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015
+# Purna Chandra Mandal, purna.mandal@microchip.com.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+obj-y := pic32mzda.o ddr.o
diff --git a/board/microchip/pic32mzda/README b/board/microchip/pic32mzda/README
new file mode 100644
index 0000000..ccf6dcb
--- /dev/null
+++ b/board/microchip/pic32mzda/README
@@ -0,0 +1,22 @@
+/*
+ * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
+ */
+
+PIC32MZ[DA] Starter-Kit
+----------------------------------------
+PIC32MZ[DA] Starter Kit is based on PIC32MZ[DA] family of micro-controller.
+This family is powered by MIPS M14KEC 32bit general purpose core with advanced
+microcontroller features and peripherals.
+
+This processor boots with proprietary stage1 bootloader running from on-chip
+boot-flash. Stage1 bootloader locates and jumps to U-Boot programmed on
+another onchip program flash. Finally U-Boot locates and loads OS image
+(along with other required files for booting) from either uSD card, or
+ethernet, or from USB storage connected on-chip USB controller.
+
+To boot Linux following three files are mandatory - uEnv.txt (custom U-Boot
+environment file), uImage, *.dtb (platform device-tree-blob file).
+
+U-Boot jumps to Linux using UHI specification.
+
+Visit http://microchip.com for details.
diff --git a/board/microchip/pic32mzda/config.mk b/board/microchip/pic32mzda/config.mk
new file mode 100644
index 0000000..a12e712
--- /dev/null
+++ b/board/microchip/pic32mzda/config.mk
@@ -0,0 +1,4 @@
+#
+# Microchip PIC32MZ[DA] board (PIC32 SoC powered by MIPS M14KEc CPU)
+#
+CONFIG_SYS_TEXT_BASE = 0x9d004000
diff --git a/board/microchip/pic32mzda/ddr.c b/board/microchip/pic32mzda/ddr.c
new file mode 100644
index 0000000..31a44fa
--- /dev/null
+++ b/board/microchip/pic32mzda/ddr.c
@@ -0,0 +1,389 @@
+/*
+ * (c) 2015 Paul Thacker <paul.thacker@microchip.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */
+
+#include <asm/io.h>
+#include <stdint.h>
+#include <config.h>
+#include <linux/kernel.h>
+#include <asm/mipsregs.h>
+#include <asm/arch-pic32/pic32.h>
+
+#include "ddr.h"
+
+/* macros */
+#define hc_clk_dly(dly)        \
+    (max_t(u32, (DIV_ROUND_UP((dly), CLK_PERIOD)), 2) - 2)
+
+/* Host Commands */
+#define IDLE_NOP        0x00FFFFFF
+#define PRECH_ALL_CMD        0x00FFF401
+#define REF_CMD            0x00FFF801
+#define LOAD_MODE_CMD        0x00FFF001
+#define CKE_LOW            0x00FFEFFE
+
+#define NUM_HOST_CMDS        12
+
+/* DDR address decoding */
+#define COL_HI_RSHFT        0
+#define COL_HI_MASK        0
+#define COL_LO_MASK        ((1 << COL_BITS) - 1)
+
+#define BA_RSHFT        COL_BITS
+#define BANK_ADDR_MASK        ((1 << BA_BITS) - 1)
+
+#define ROW_ADDR_RSHIFT        (BA_RSHFT + BA_BITS)
+#define ROW_ADDR_MASK        ((1 << ROW_BITS) - 1)
+
+#define CS_ADDR_RSHIFT        0
+#define CS_ADDR_MASK        0
+
+/* MPLL freq is 400MHz */
+#define CLK_PERIOD              2500    /* 2500 psec */
+#define CTRL_CLK_PERIOD         (CLK_PERIOD * 2)
+
+/* Arbiter */
+#define NUM_AGENTS              5
+#define MIN_LIM_WIDTH           5
+#define RQST_PERIOD_WIDTH       8
+#define MIN_CMDACPT_WIDTH       8
+
+#define EN_AUTO_PRECH           0
+#define SB_PRI                  1
+#define BIG_ENDIAN              0
+#define HALF_RATE_MODE          1
+
+/*****************************************************************************/
+/* DDR definitions */
+/*****************************************************************************/
+
+/* DDR Address Mapping: CS, ROW, BA, COL */
+#define COL_BITS    10
+#define ROW_BITS    13
+#define BA_BITS        3
+#define CS_BITS        1
+
+/* DDR constants */
+#define BL        2    /* Burst length in cycles */
+
+/* default CAS latency for all speed grades */
+#define RL        5
+
+/* default write latency for all speed grades = CL-1 */
+#define WL        4
+
+#define MAX_BURST    3
+
+/* NOTE: DDR data from Micron MT47H64M16HR-3 data sheet */
+#define tRFC_MIN    127500    /* psec */
+#define tWR        15000    /* psec */
+#define tRP        12500    /* psec */
+#define tRCD        12500    /* psec */
+#define tRRD        7500    /* psec */
+
+/* tRRD_TCK is a minimum of 2 clk periods, regardless of clk freq */
+#define tRRD_TCK    2
+#define tWTR        7500    /* psec */
+
+/* tWTR_TCK is a minimum of 2 clk periods, regardless of clk freq */
+#define tWTR_TCK    2
+#define tRTP        7500    /* psec */
+#define tRTP_TCK    (BL / 2)
+#define tXP_TCK        2    /* clocks */
+#define tCKE_TCK    3    /* clocks */
+#define tXSNR        (tRFC_MIN + 10000) /* psec */
+#define tDLLK        200     /* clocks */
+#define tRAS_MIN    45000   /* psec */
+#define tRC        57500   /* psec */
+#define tFAW        35000   /* psec */
+#define tMRD        2       /* clocks */
+#define tRFI        7800000 /* psec */
+
+/* Refresh Config */
+#define MAX_PEND_REF        7
+
+/* Power Config */
+#define PRECH_PWR_DN_ONLY    0
+#define SELF_REF_DLY        17
+#define PWR_DN_DLY        8
+#define EN_AUTO_SELF_REF    0
+#define EN_AUTO_PWR_DN        0
+#define ERR_CORR_EN        0
+#define ECC_EN            0
+
+/* PHY PAD CONTROL */
+#define ODT_SEL            1
+#define ODT_EN            1
+#define DRIVE_SEL        0
+#define ODT_PD            2
+#define ODT_PU            3
+#define EXTRA_OEN_CLK        0
+#define NOEXT_DLL        1
+#define HALF_RATE        1
+#define DLR_DFI_WRCMD        1
+#define DRVSTR_PFET        0xE
+#define DRVSTR_NFET        0xE
+#define RCVR_EN            1
+#define PREAMBLE_DLY        2
+
+/* PHY DLL RECALIBRATE */
+#define RECALIB_CNT        0x10
+#define DELAY_START_VAL        3
+
+/* SCL CONFIG */
+#define SCL_BURST8        1
+#define SCL_DDR2_CONNECTED    1
+#define SCL_ODTCSWW        1
+#define SCL_CSEN        1
+#define SCL_CAPCLKDLY        3
+#define SCL_DDRCLKDLY        4
+
+/* SCL START */
+#define SCL_START        0x10000000
+#define SCL_EN            0x04000000
+#define SCL_LUBPASS        3
+
+void ddr_pmd_unlock(void)
+{
+    writel(0, PMD7);
+}
+
+/* init DDR2 Phy */
+void ddr_phy_init(void)
+{
+    u32 phy_pad_ctl;
+
+    /* Enable DDR peripheral (disabled by default) */
+    ddr_pmd_unlock();
+
+    /* PHY_DLL_RECALIB */
+    writel((DELAY_START_VAL << 28) | (RECALIB_CNT << 8), DDR2PHYDLLR);
+
+    phy_pad_ctl = (ODT_SEL | (ODT_EN << 1) | (DRIVE_SEL << 2) |
+               (ODT_PD << 4) | (ODT_PU << 6) |
+               (EXTRA_OEN_CLK << 8) | (NOEXT_DLL << 9) |
+               (DLR_DFI_WRCMD << 13) | (HALF_RATE << 14) |
+               (DRVSTR_PFET << 16) | (DRVSTR_NFET << 20) |
+               (RCVR_EN << 28) | (PREAMBLE_DLY << 29));
+
+    /* PHY_PAD_CTRL */
+    writel(phy_pad_ctl, DDR2PHYPADCON);
+
+    /* SCL_CONFIG_0 */
+    writel(SCL_BURST8 | (SCL_DDR2_CONNECTED << 1) | (RL << 4) |
+           (SCL_ODTCSWW << 24), DDR2SCLCFG0);
+
+    /* SCL_CONFIG_1 */
+    writel(SCL_CSEN | (WL << 8), DDR2SCLCFG1);
+
+    /* SCLLAT */
+    writel(SCL_CAPCLKDLY | (SCL_DDRCLKDLY << 4), DDR2SCLLAT);
+}
+
+/* init DDR2 Controller */
+void ddr_init(void)
+{
+    u32 v;
+    u32 wr2prech, rd2prech, wr2rd, wr2rd_csc;
+    u32 ras2ras, ras2cas, prech2ras;
+    u32 ba_field, ma_field;
+
+    /* MEM_WIDTH */
+    writel(HALF_RATE_MODE << 3, DDR2MEMWIDTH);
+
+    /* Set arbiter configuration per target */
+    writel(0 * MIN_LIM_WIDTH, DDR2TSEL);
+    writel(0x1f, DDR2MINLIM);
+    writel(0 * RQST_PERIOD_WIDTH, DDR2TSEL);
+    writel(0xff, DDR2REQPRD);
+    writel(0 * MIN_CMDACPT_WIDTH, DDR2TSEL);
+    writel(0x04, DDR2MINCMD);
+
+    writel(1 * MIN_LIM_WIDTH, DDR2TSEL);
+    writel(0x1f, DDR2MINLIM);
+    writel(1 * RQST_PERIOD_WIDTH, DDR2TSEL);
+    writel(0xff, DDR2REQPRD);
+    writel(1 * MIN_CMDACPT_WIDTH, DDR2TSEL);
+    writel(0x10, DDR2MINCMD);
+
+    writel(2 * MIN_LIM_WIDTH, DDR2TSEL);
+    writel(0x1f, DDR2MINLIM);
+    writel(2 * RQST_PERIOD_WIDTH, DDR2TSEL);
+    writel(0xff, DDR2REQPRD);
+    writel(2 * MIN_CMDACPT_WIDTH, DDR2TSEL);
+    writel(0x10, DDR2MINCMD);
+
+    writel(3 * MIN_LIM_WIDTH, DDR2TSEL);
+    writel(0x04, DDR2MINLIM);
+    writel(3 * RQST_PERIOD_WIDTH, DDR2TSEL);
+    writel(0xff, DDR2REQPRD);
+    writel(3 * MIN_CMDACPT_WIDTH, DDR2TSEL);
+    writel(0x04, DDR2MINCMD);
+
+    writel(4 * MIN_LIM_WIDTH, DDR2TSEL);
+    writel(0x04, DDR2MINLIM);
+    writel(4 * RQST_PERIOD_WIDTH, DDR2TSEL);
+    writel(0xff, DDR2REQPRD);
+    writel(4 * MIN_CMDACPT_WIDTH, DDR2TSEL);
+    writel(0x04, DDR2MINCMD);
+
+    /* Address Configuration */
+    writel((ROW_ADDR_RSHIFT | (BA_RSHFT << 8) | (CS_ADDR_RSHIFT << 16) |
+           (COL_HI_RSHFT << 24) | (SB_PRI << 29)  |
+           (EN_AUTO_PRECH << 30)), DDR2MEMCFG0);
+    writel(ROW_ADDR_MASK, DDR2MEMCFG1);
+    writel(COL_HI_MASK, DDR2MEMCFG2);
+    writel(COL_LO_MASK, DDR2MEMCFG3);
+    writel((BANK_ADDR_MASK | (CS_ADDR_MASK << 8)), DDR2MEMCFG4);
+
+    /* Refresh Config */
+    writel((DIV_ROUND_UP(tRFI, CTRL_CLK_PERIOD) - 2) |
+           ((DIV_ROUND_UP(tRFC_MIN, CTRL_CLK_PERIOD) - 2) << 16) |
+           (MAX_PEND_REF << 24), DDR2REFCFG);
+
+    /* Power Config */
+    writel((ECC_EN | (ERR_CORR_EN << 1) | (EN_AUTO_PWR_DN << 2) |
+           (EN_AUTO_SELF_REF << 3) | (PWR_DN_DLY << 4) |
+           (SELF_REF_DLY << 12) | (PRECH_PWR_DN_ONLY << 22)),
+           DDR2PWRCFG);
+
+    /* Delay Config */
+    wr2rd = max_t(u32, DIV_ROUND_UP(tWTR, CTRL_CLK_PERIOD),
+              DIV_ROUND_UP(tWTR_TCK, 2)) + WL + BL;
+    wr2rd_csc = max_t(u32, wr2rd - 1, 3);
+    wr2prech = DIV_ROUND_UP(tWR, CTRL_CLK_PERIOD) + (WL + BL);
+    rd2prech = max_t(u32, DIV_ROUND_UP(tRTP, CTRL_CLK_PERIOD),
+             DIV_ROUND_UP(tRTP_TCK, 2)) + BL - 2;
+    ras2ras = max_t(u32, DIV_ROUND_UP(tRRD, CTRL_CLK_PERIOD),
+            DIV_ROUND_UP(tRRD_TCK, 2)) - 1;
+    ras2cas = DIV_ROUND_UP(tRCD, CTRL_CLK_PERIOD) - 1;
+    prech2ras = DIV_ROUND_UP(tRP, CTRL_CLK_PERIOD) - 1;
+
+    writel(((wr2rd & 0x0F) | ((wr2rd_csc & 0x0F) << 4) |
+           ((BL - 1) << 8) | (BL << 12) | ((BL - 1) << 16) |
+           ((BL - 1) << 20) | ((BL + 2) << 24) |
+           ((RL - WL + 3) << 28)), DDR2DLYCFG0);
+
+    writel(((tCKE_TCK - 1) | (((DIV_ROUND_UP(tDLLK, 2) - 2) & 0xFF) << 8) |
+           ((tCKE_TCK - 1) << 16) |
+           ((max_t(u32, tXP_TCK, tCKE_TCK) - 1) << 20) |
+           ((wr2prech >> 4) << 26) | ((wr2rd >> 4) << 27) |
+           ((wr2rd_csc >> 4) << 28) | (((RL + 5) >> 4) << 29) |
+           ((DIV_ROUND_UP(tDLLK, 2) >> 8) << 30)), DDR2DLYCFG1);
+
+    writel((DIV_ROUND_UP(tRP, CTRL_CLK_PERIOD) | (rd2prech << 8) |
+           ((wr2prech & 0x0F) << 12) | (ras2ras << 16) | (ras2cas << 20) |
+           (prech2ras << 24) | ((RL + 3) << 28)), DDR2DLYCFG2);
+
+    writel(((DIV_ROUND_UP(tRAS_MIN, CTRL_CLK_PERIOD) - 1) |
+           ((DIV_ROUND_UP(tRC, CTRL_CLK_PERIOD) - 1) << 8) |
+           ((DIV_ROUND_UP(tFAW, CTRL_CLK_PERIOD) - 1) << 16)),
+           DDR2DLYCFG3);
+
+    /* ODT Config */
+    writel(0x00000000, DDR2ODTCFG);
+    writel(0x00010000, DDR2ODTENCFG);/* WREN on CS */
+
+    writel(((RL - 3) << 8) | ((WL - 3) << 12) | (2 << 16) | (3 << 20),
+           DDR2ODTCFG);
+
+    /* TODO: resolve differences in NXTDATRQDLY, NXDATAVDLY and RDATENDLY */
+    writel(/*(WL - 1)*/2 | (/*((RL + 1) & 0x0F)*/4  << 4) |
+           (/*(RL - 1)*/2 << 16) |
+           (MAX_BURST << 24) | (7 << 28) | (BIG_ENDIAN << 31),
+           DDR2XFERCFG);
+
+    /* DRAM Initialization */
+    /* bring CKE high after reset and wait 400 nsec */
+    writel(IDLE_NOP, DDR2CMD10);
+    writel((0x00 | (0x00 << 8) | (hc_clk_dly(400000) << 11)),
+           DDR2CMD20);
+
+    /* issue precharge all command */
+    writel(PRECH_ALL_CMD, DDR2CMD10 + 0x04);
+    writel((0x04 | (0x00 << 8) | (hc_clk_dly(tRP + CLK_PERIOD) << 11)),
+           DDR2CMD20 + 0x04);
+
+    /* initialize EMR2 */
+    writel(LOAD_MODE_CMD, DDR2CMD10 + 0x08);
+    writel((0x00 | (0x02 << 8) | (hc_clk_dly(tMRD * CLK_PERIOD) << 11)),
+           DDR2CMD20 + 0x08);
+
+    /* initialize EMR3 */
+    writel(LOAD_MODE_CMD, DDR2CMD10 + 0x0C);
+    writel((0x00 | (0x03 << 8) | (hc_clk_dly(tMRD * CLK_PERIOD) << 11)),
+           DDR2CMD20 + 0x0C);
+
+    /*
+     * RDQS disable, DQSB enable, OCD exit, 150 ohm termination,
+     * AL=0, DLL enable
+     */
+    writel((LOAD_MODE_CMD | (0x40 << 24)), DDR2CMD10 + 0x10);
+    writel((0x00 | (0x01 << 8) | (hc_clk_dly(tMRD * CLK_PERIOD) << 11)),
+           DDR2CMD20 + 0x10);
+
+    v = ((DIV_ROUND_UP(tWR, CLK_PERIOD) - 1) << 1) | 1;
+    ma_field = v & 0xFF;
+    ba_field = (v >> 8) & 0x03;
+
+    /*
+     * PD fast exit, WR REC = tWR in clocks -1,
+     * DLL reset, CAS = RL, burst = 4
+     */
+    writel((LOAD_MODE_CMD | (((RL << 4) | 2) << 24)), DDR2CMD10 + 0x14);
+    writel((ma_field | (ba_field << 8) |
+           (hc_clk_dly(tMRD * CLK_PERIOD) << 11)), DDR2CMD20 + 0x14);
+
+    /* issue precharge all command */
+    writel(PRECH_ALL_CMD, DDR2CMD10 + 0x18);
+    writel((0x04 | (0x00 << 8) | (hc_clk_dly(tRP + CLK_PERIOD) << 11)),
+           DDR2CMD20 + 0x18);
+
+    /* issue refresh command */
+    writel(REF_CMD, DDR2CMD10 + 0x1C);
+    writel((0x00 | (0x00 << 8) | (hc_clk_dly(tRFC_MIN) << 11)),
+           DDR2CMD20 + 0x1C);
+
+    /* issue refresh command */
+    writel(REF_CMD, DDR2CMD10 + 0x20);
+    writel((0x00 | (0x00 << 8) | (hc_clk_dly(tRFC_MIN) << 11)),
+           DDR2CMD20 + 0x20);
+
+    /* Mode register programming as before without DLL reset */
+    writel((((RL << 4) | 3) << 24) | LOAD_MODE_CMD, DDR2CMD10 + 0x24);
+
+    v = ((DIV_ROUND_UP(tWR, CLK_PERIOD) - 1) << 1);
+    ma_field = v & 0xFF;
+    ba_field = (v >> 8) & 0x03;
+
+    writel((ma_field | (ba_field << 8) |
+           (hc_clk_dly(tMRD * CLK_PERIOD) << 11)), DDR2CMD20 + 0x24);
+
+    /* extended mode register same as before with OCD default */
+    writel((LOAD_MODE_CMD | (0xC0 << 24)), DDR2CMD10 + 0x28);
+    writel((0x03 | (0x01 << 8) | (hc_clk_dly(tMRD * CLK_PERIOD) << 11)),
+           DDR2CMD20 + 0x28);
+
+    /* extended mode register same as before with OCD exit */
+    writel((LOAD_MODE_CMD | (0x40 << 24)), DDR2CMD10 + 0x2C);
+    writel((0x00 | (0x01 << 8) | (hc_clk_dly(140 * CLK_PERIOD) << 11)),
+           DDR2CMD20 + 0x2C);
+
+    writel(0x1B, DDR2CMDISSUE);
+    writel(0x01, DDR2MEMCON);
+
+    while (readl(DDR2CMDISSUE) & 0x10)
+        ;
+
+    writel(0x03, DDR2MEMCON);
+
+    /* SCL Start */
+    writel(SCL_START | SCL_EN, DDR2SCLSTART);
+
+    /* Wait for SCL byte to pass */
+    while ((readl(DDR2SCLSTART) & SCL_LUBPASS) != SCL_LUBPASS)
+        ;
+}
diff --git a/board/microchip/pic32mzda/ddr.h b/board/microchip/pic32mzda/ddr.h
new file mode 100644
index 0000000..7828169
--- /dev/null
+++ b/board/microchip/pic32mzda/ddr.h
@@ -0,0 +1,46 @@
+/*
+ * (c) 2015 Purna Chandra Mandal purna.mandal@microchip.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */
+
+#ifndef __PIC32MZDA_DDR_H
+#define __PIC32MZDA_DDR_H
+
+#define DDR2TSEL    (PIC32_DDR2C_BASE + 0x00) /* ARB_AGENT_SEL       */
+#define DDR2MINLIM    (PIC32_DDR2C_BASE + 0x04) /* MIN_LIMIT           */
+#define DDR2REQPRD    (PIC32_DDR2C_BASE + 0x08) /* RQST_PERIOD         */
+#define DDR2MINCMD    (PIC32_DDR2C_BASE + 0x0c) /* MIN_CMD_ACPT        */
+#define DDR2MEMCON    (PIC32_DDR2C_BASE + 0x10) /* MEM_START           */
+#define DDR2MEMCFG0    (PIC32_DDR2C_BASE + 0x14) /* MEM_CONFIG_1        */
+#define DDR2MEMCFG1    (PIC32_DDR2C_BASE + 0x18) /* MEM_CONFIG_2        */
+#define DDR2MEMCFG2    (PIC32_DDR2C_BASE + 0x1c) /* MEM_CONFIG_3        */
+#define DDR2MEMCFG3    (PIC32_DDR2C_BASE + 0x20) /* MEM_CONFIG_4        */
+#define DDR2MEMCFG4    (PIC32_DDR2C_BASE + 0x24) /* MEM_CONFIG_5        */
+#define DDR2REFCFG    (PIC32_DDR2C_BASE + 0x28) /* REF_CONFIG          */
+#define DDR2PWRCFG    (PIC32_DDR2C_BASE + 0x2c) /* PWR_SAVE_ECC_CONFIG */
+#define DDR2DLYCFG0    (PIC32_DDR2C_BASE + 0x30) /* DLY_CONFIG1         */
+#define DDR2DLYCFG1    (PIC32_DDR2C_BASE + 0x34) /* DLY_CONFIG2         */
+#define DDR2DLYCFG2    (PIC32_DDR2C_BASE + 0x38) /* DLY_CONFIG3         */
+#define DDR2DLYCFG3    (PIC32_DDR2C_BASE + 0x3c) /* DLY_CONFIG4         */
+#define DDR2ODTCFG    (PIC32_DDR2C_BASE + 0x40) /* ODT_CONFIG          */
+#define DDR2XFERCFG    (PIC32_DDR2C_BASE + 0x44) /* DATA_XFR_CONFIG     */
+#define DDR2CMDISSUE    (PIC32_DDR2C_BASE + 0x48) /* HOST_CMD_ISSUE      */
+#define DDR2ODTENCFG    (PIC32_DDR2C_BASE + 0x4c) /* ODT_EN_CONFIG       */
+#define DDR2MEMWIDTH    (PIC32_DDR2C_BASE + 0x50) /* MEM_WIDTH           */
+#define DDR2CMD10    (PIC32_DDR2C_BASE + 0x80) /* HOST_CMD1           */
+#define DDR2CMD20    (PIC32_DDR2C_BASE + 0xc0) /* HOST_CMD2           */
+
+/* DDR PHY */
+#define DDR2SCLSTART    (PIC32_DDR2P_BASE + 0x00) /* SCL_START           */
+#define DDR2SCLLAT    (PIC32_DDR2P_BASE + 0x0c) /* PHY_SCLLAAT         */
+#define DDR2SCLCFG0    (PIC32_DDR2P_BASE + 0x18) /* SCL_CONFIG_1        */
+#define DDR2SCLCFG1    (PIC32_DDR2P_BASE + 0x1c) /* SCL_CONFIG_2        */
+#define DDR2PHYPADCON    (PIC32_DDR2P_BASE + 0x20) /* PHY_PAD_CTRL        */
+#define DDR2PHYDLLR    (PIC32_DDR2P_BASE + 0x24) /* PHY_DLL_RECALIB     */
+
+void ddr_phy_init(void);
+void ddr_init(void);
+
+#endif    /* __PIC32MZDA_DDR_H */
diff --git a/board/microchip/pic32mzda/pic32mzda.c b/board/microchip/pic32mzda/pic32mzda.c
new file mode 100644
index 0000000..ad312b2
--- /dev/null
+++ b/board/microchip/pic32mzda/pic32mzda.c
@@ -0,0 +1,41 @@
+/*
+ * Microchip PIC32MZ[DA] Starter Kit board
+ *
+ * Copyright (C) 2015, Microchip Technology Inc.
+ * Purna Chandra Mandal <purna.mandal@microchip.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <clk.h>
+#include <asm/arch-pic32/pic32.h>
+
+#include "ddr.h"
+
+/* initialize the DDR and PHY */
+phys_size_t initdram(int board_type)
+{
+    ddr_phy_init();
+    ddr_init();
+    return CONFIG_SYS_MEM_SIZE;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+    ulong rate = 0;
+    struct udevice *dev;
+
+    printf("Core: %s\n", get_core_name());
+
+    if (!uclass_get_device(UCLASS_CLK, 0, &dev)) {
+        rate = clk_get_rate(dev);
+        printf("CPU Speed: %lu MHz\n", rate / 1000000);
+    }
+
+    return 0;
+}
+#endif
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
new file mode 100644
index 0000000..df06f8b
--- /dev/null
+++ b/configs/pic32mzdask_defconfig
@@ -0,0 +1,22 @@
+CONFIG_MIPS=y
+CONFIG_MACH_PIC32=y
+CONFIG_SOC_PIC32MZDA=y
+CONFIG_TARGET_PIC32MZDASK=y
+CONFIG_PIC32_SUPPORTS_FDT_BOOT=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="dask # "
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_SUPPORT_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk"
+CONFIG_DM=y
+CONFIG_CMD_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_PIC32_SERIAL=y
+CONFIG_CLK=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_FULL is not set
+CONFIG_PIC32_PINCTRL=y
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
new file mode 100644
index 0000000..9f867ed
--- /dev/null
+++ b/include/configs/pic32mzdask.h
@@ -0,0 +1,110 @@
+/*
+ * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ * Microchip PIC32MZ[DA] StarterKit.
+ */
+
+#ifndef __PIC32MZDASK_CONFIG_H
+#define __PIC32MZDASK_CONFIG_H
+
+/* System Configuration */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*--------------------------------------------
+ * CPU configuration
+ */
+#define CONFIG_MIPS            1
+#define CONFIG_MIPS32        1  /* MIPS32 CPU core    */
+
+/* CPU Timer rate */
+#define CONFIG_SYS_MIPS_TIMER_FREQ    100000000
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE        32768
+#define CONFIG_SYS_ICACHE_SIZE        32768
+#define CONFIG_SYS_CACHELINE_SIZE    16
+#define CONFIG_SYS_MIPS_CACHE_MODE    CONF_CM_CACHABLE_NONCOHERENT
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*----------------------------------------------------------------------
+ * Memory Layout
+ */
+#define CONFIG_SYS_SRAM_BASE        0x80000000
+#define CONFIG_SYS_SRAM_SIZE        0x00080000 /* 512K in PIC32MZSK */
+
+/* Initial RAM for temporary stack, global data */
+#define CONFIG_SYS_INIT_RAM_SIZE    0x10000
+#define CONFIG_SYS_INIT_RAM_ADDR    \
+    (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    \
+    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_SP_ADDR        \
+    (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* SDRAM Configuration (for final code, data, stack, heap) */
+#define CONFIG_SYS_SDRAM_BASE        0x88000000
+#define CONFIG_SYS_MEM_SIZE        (128 << 20) /* 128M */
+
+#define CONFIG_SYS_MALLOC_LEN        (256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN    (4 << 10)
+#define CONFIG_STACKSIZE        (4 << 10) /* regular stack */
+#define CONFIG_SYS_EXCEPTION_ADDR    0xA000100 /* EBASE ADDR */
+
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN        (192 << 10)
+
+#define CONFIG_SYS_LOAD_ADDR        0x88500000 /* default load address */
+#define CONFIG_SYS_ENV_ADDR        0x88300000
+
+/* Memory Test */
+#define CONFIG_SYS_MEMTEST_START    0x88000000
+#define CONFIG_SYS_MEMTEST_END        0x88080000
+
+/*----------------------------------------------------------------------
+ * Commands
+ */
+#define CONFIG_SYS_LONGHELP        /* undef to save memory */
+#define CONFIG_CMD_CLK
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_CMD_MEMINFO
+
+/*-------------------------------------------------
+ * FLASH configuration
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*------------------------------------------------------------
+ * Console Configuration
+ */
+#define CONFIG_BAUDRATE            115200
+#define CONFIG_SYS_BAUDRATE_TABLE    {9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_CBSIZE        1024 /* Console I/O Buffer Size   */
+#define CONFIG_SYS_MAXARGS        16   /* max number of command args*/
+#define CONFIG_SYS_PBSIZE        \
+        (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_CMDLINE_EDITING        1
+
+/*
+ * Handover flattened device tree (dtb file) to Linux kernel
+ */
+#define CONFIG_OF_LIBFDT    1
+
+/* -------------------------------------------------
+ * Environment
+ */
+#define CONFIG_ENV_IS_NOWHERE    1
+#define CONFIG_ENV_SIZE        0x4000
+
+/* ---------------------------------------------------------------------
+ * Board boot configuration
+ */
+#define CONFIG_TIMESTAMP    /* Print image info with timestamp */
+#define CONFIG_BOOTDELAY    5 /* autoboot after X seconds     */
+#undef    CONFIG_BOOTARGS
+
+#define CONFIG_MEMSIZE_IN_BYTES        /* pass 'memsize=' in bytes */
+#endif    /* __PIC32MZDASK_CONFIG_H */
