diff mbox

[U-Boot,2/3] zynq: slcr: Wait 100ms till clk is properly setup

Message ID 552e3da817892844787783580457bcd283a2eb7f.1374761918.git.michal.simek@xilinx.com
State Superseded
Delegated to: Albert ARIBAUD
Headers show

Commit Message

Michal Simek July 25, 2013, 2:18 p.m. UTC 
If you don't wait you will loose the first sent packet
even all bits in emacps are correctly setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 arch/arm/cpu/armv7/zynq/slcr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--
1.8.2.3
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 52048c6..1c28e96 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -86,7 +86,7 @@  void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
 		/* Configure GEM_RCLK_CTRL */
 		writel(rclk, &slcr_base->gem0_rclk_ctrl);
 	}
-
+	udelay(100000);
 out:
 	zynq_slcr_lock();
 }