From patchwork Mon May 14 19:45:23 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Troy Kisky X-Patchwork-Id: 159133 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id E3AD0B7032 for ; Tue, 15 May 2012 05:45:35 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A099128085; Mon, 14 May 2012 21:45:32 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uA48xfdy3RMM; Mon, 14 May 2012 21:45:32 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0D69928081; Mon, 14 May 2012 21:45:30 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D12EF28081 for ; Mon, 14 May 2012 21:45:26 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HVBRqhNnkI-P for ; Mon, 14 May 2012 21:45:25 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from oproxy6-pub.bluehost.com (oproxy6-pub.bluehost.com [67.222.54.6]) by theia.denx.de (Postfix) with SMTP id 5DC6F28080 for ; Mon, 14 May 2012 21:45:22 +0200 (CEST) Received: (qmail 4667 invoked by uid 0); 14 May 2012 19:45:21 -0000 Received: from unknown (HELO box284.bluehost.com) (69.89.31.84) by cpoproxy3.bluehost.com with SMTP; 14 May 2012 19:45:21 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=boundarydevices.com; s=default; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:References:Subject:CC:To:MIME-Version:From:Date:Message-ID; bh=MqhqcGcURg/rGa9Gav40ZXGBxk1ILUdqUX+epzG37TA=; b=PikBYVwN7M1szR5oq+862OO+RqzFxxPubH0G7V840sAbbmE7omicCDvN6+KGeV8vx5vzrKa6j/d8NSetQcJYo7NpW6m4bVF0rBK8XD2NXrO350g5m3e0jpvA9FiaOgEL; Received: from [70.96.116.236] (helo=[192.168.64.114]) by box284.bluehost.com with esmtpsa (TLSv1:CAMELLIA256-SHA:256) (Exim 4.76) (envelope-from ) id 1SU1Cr-0003br-BC; Mon, 14 May 2012 13:45:21 -0600 Message-ID: <4FB160D3.6020807@boundarydevices.com> Date: Mon, 14 May 2012 12:45:23 -0700 From: Troy Kisky User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:12.0) Gecko/20120428 Thunderbird/12.0.1 MIME-Version: 1.0 To: Fabio Estevam References: In-Reply-To: X-Identified-User: {1412:box284.bluehost.com:boundar4:boundarydevices.com} {sentby:smtp auth 70.96.116.236 authed with troy.kisky@boundarydevices.com} Cc: U-Boot-Denx Subject: Re: [U-Boot] Framebuffer support hangs kernel on mx53loco X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de On 5/14/2012 10:27 AM, Fabio Estevam wrote: > Hi Stefano/Anatolij, > > When I activate framebuffer support for mx53loco board I face the > following problem (in about half of my attempts to boot the kernel): > > Starting kernel ... > > Linux version 2.6.35.3-01129-g691c08a (fabio@fabio-Latitude-E6410) > (gcc version 4.4.4 (4.4.4_09.06.2010) ) #5 PREEMPT Mon May 14 14:22:49 > BRT 2012 > CPU: ARMv7 Processor [412fc085] revision 5 (ARMv7), cr=10c53c7f > CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache > Machine: Freescale MX53 LOCO Board > Memory policy: ECC disabled, Data cache writeback > Built 1 zonelists in Zone order, mobility grouping on. Total pages: 250880 > Kernel command line: console=ttymxc0,115200 root=/dev/nfs ip=dhcp > nfsroot=10.29.240.143:,v3,tcp > PID hash table entries: 4096 (order: 2, 16384 bytes) > Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) > Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) > Memory: 480MB 512MB = 992MB total > Memory: 998528k/998528k available, 17280k reserved, 0K highmem > Virtual kernel memory layout: > vector : 0xffff0000 - 0xffff1000 ( 4 kB) > fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) > DMA : 0xf9e00000 - 0xffe00000 ( 96 MB) > vmalloc : 0xe0800000 - 0xf4000000 ( 312 MB) > lowmem : 0x80000000 - 0xe0000000 (1536 MB) > pkmap : 0x7fe00000 - 0x80000000 ( 2 MB) > modules : 0x7f000000 - 0x7fe00000 ( 14 MB) > .init : 0x80008000 - 0x80032000 ( 168 kB) > .text : 0x80032000 - 0x807b4000 (7688 kB) > .data : 0x807d0000 - 0x808234c0 ( 334 kB) > SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 > Hierarchical RCU implementation. > RCU-based detection of stalled CPUs is disabled. > Verbose stalled-CPUs detection is disabled. > NR_IRQS:368 > MXC GPIO hardware > MXC IRQ initialized > MXC_Early serial console at MMIO 0x53fbc000 (options '115200') > bootconsole [ttymxc0] enabled > Console: colour dummy device 80x30 > Calibrating delay loop... 799.53 BogoMIPS (lpj=3997696) > pid_max: default: 32768 minimum: 301 > Mount-cache hash table entries: 512 > CPU: Testing write buffer coherency: ok > regulator: core version 0.5 > NET: Registered protocol family 16 > i.MX IRAM pool: 128 KB@0xe0840000 > IRAM READY > CPU is i.MX53 Revision 2.1 > > (system hangs here) > > When framebuffer is not used I can succesfully reboot the board several times. > > I know it is a difficult question, but in case you have any > ideas/suggestions I would be glad to listen to. > > Regards, > > Fabio Estevam > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > This patch (though you can't apply it directly) may give you a clue. Author: Troy Kisky Date: Tue Jan 24 14:46:29 2012 -0700 squash with dont_sleep, fix non-lvds boot { @@ -4590,6 +4603,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long int wp_cnt = 0; u32 pll1_rate; + turn_off_display(MX51_IPU_CTRL_BASE_ADDR + ((512 - 32) << 20)); pll1_base = ioremap(PLL1_BASE_ADDR, SZ_4K); pll2_base = ioremap(PLL2_BASE_ADDR, SZ_4K); pll3_base = ioremap(PLL3_BASE_ADDR, SZ_4K); @@ -4622,9 +4636,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long __raw_writel(0, MXC_CCM_CCGR3); __raw_writel(1 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR4); - /* if ipu enabled, leave enabled, else sleep handshake will fail */ - reg = __raw_readl(MXC_CCM_CCGR5) & (3 << MXC_CCM_CCGRx_CG5_OFFSET); - __raw_writel(reg | 1 << MXC_CCM_CCGRx_CG2_OFFSET | + __raw_writel(1 << MXC_CCM_CCGRx_CG2_OFFSET | 1 << MXC_CCM_CCGR5_CG6_1_OFFSET | 1 << MXC_CCM_CCGR5_CG6_2_OFFSET | 3 << MXC_CCM_CCGRx_CG7_OFFSET | @@ -4910,6 +4922,8 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long int i = 0, j = 0, reg; u32 pll1_rate; + turn_off_display(MX53_IPU_CTRL_BASE_ADDR + ((128 - 32) << 20)); + pll1_base = ioremap(MX53_BASE_ADDR(PLL1_BASE_ADDR), SZ_4K); pll2_base = ioremap(MX53_BASE_ADDR(PLL2_BASE_ADDR), SZ_4K); pll3_base = ioremap(MX53_BASE_ADDR(PLL3_BASE_ADDR), SZ_4K); @@ -4955,9 +4969,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long __raw_writel(0, MXC_CCM_CCGR3); __raw_writel(1 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR4); - /* if ipu enabled, leave enabled, else sleep handshake will fail */ - reg = __raw_readl(MXC_CCM_CCGR5) & (3 << MXC_CCM_CCGRx_CG5_OFFSET); - __raw_writel(reg | 1 << MXC_CCM_CCGRx_CG2_OFFSET | + __raw_writel(1 << MXC_CCM_CCGRx_CG2_OFFSET | 1 << MXC_CCM_CCGRx_CG6_OFFSET | 3 << MXC_CCM_CCGRx_CG7_OFFSET | 1 << MXC_CCM_CCGRx_CG8_OFFSET | diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c index faecc34..efe324c 100644 --- a/arch/arm/mach-mx5/clock.c +++ b/arch/arm/mach-mx5/clock.c @@ -4581,6 +4581,19 @@ static void clk_tree_init(void) } } +#define IPU_CONF 0x000 +#define IPU_DISP_GEN 0x0C4 + +void turn_off_display(int physical_base) { + void __iomem *ipuc = ioremap(physical_base, SZ_4K); + if (ipuc) { + /* clear DI0/DI1 counter release */ + unsigned reg = __raw_readl(ipuc + IPU_DISP_GEN); + __raw_writel(reg & ~(3 << 24), ipuc + IPU_DISP_GEN); + __raw_writel(0, ipuc + IPU_CONF); + iounmap(ipuc); + } +} int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2)