diff --git a/Makefile b/Makefile
index 76124e5..2bdc17b 100644
--- a/Makefile
+++ b/Makefile
@@ -808,6 +808,7 @@ at91sam9263ek_config	:	unconfig
  	fi;
  	@$(MKCONFIG) -n $@ -a at91sam9263ek arm arm926ejs at91sam9263ek atmel 
at91

+ifdef XXX
  at91sam9rlek_nandflash_config \
  at91sam9rlek_dataflash_config \
  at91sam9rlek_dataflash_cs0_config \
@@ -819,6 +820,7 @@ at91sam9rlek_config	:	unconfig
  		echo "#define CONFIG_SYS_USE_DATAFLASH 1"	>>$(obj)include/config.h ; \
  	fi;
  	@$(MKCONFIG) -n $@ -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
+endif

  CPU9G20_128M_config \
  CPU9G20_config \
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c 
b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
index 4f570f4..79ca59b 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
@@ -23,10 +23,11 @@
   */

  #include <common.h>
+#include <asm/io.h>
  #include <asm/arch/at91_common.h>
  #include <asm/arch/at91_pmc.h>
  #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+

  void at91_serial0_hw_init(void)
  {
@@ -34,7 +35,7 @@ void at91_serial0_hw_init(void)

  	at91_set_a_periph(AT91_PIO_PORTA, 6, 1);		/* TXD0 */
  	at91_set_a_periph(AT91_PIO_PORTA, 7, 0);		/* RXD0 */
-	writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer);
+	writel(1 << ATMEL_ID_US0, &pmc->pcer);
  }

  void at91_serial1_hw_init(void)
@@ -43,7 +44,7 @@ void at91_serial1_hw_init(void)

  	at91_set_a_periph(AT91_PIO_PORTA, 11, 1);		/* TXD1 */
  	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);		/* RXD1 */
-	writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer);
+	writel(1 << ATMEL_ID_US1, &pmc->pcer);
  }

  void at91_serial2_hw_init(void)
@@ -52,7 +53,7 @@ void at91_serial2_hw_init(void)

  	at91_set_a_periph(AT91_PIO_PORTA, 13, 1);		/* TXD2 */
  	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);		/* RXD2 */
-	writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer);
+	writel(1 << ATMEL_ID_US2, &pmc->pcer);
  }

  void at91_serial3_hw_init(void)
@@ -61,7 +62,7 @@ void at91_serial3_hw_init(void)

  	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);		/* DRXD */
  	at91_set_a_periph(AT91_PIO_PORTA, 22, 1);		/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
+	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
  }

  void at91_serial_hw_init(void)
@@ -93,7 +94,7 @@ void at91_spi0_hw_init(unsigned long cs_mask)
  	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* SPI0_SPCK */

  	/* Enable clock */
-	writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer);
+	writel(1 << ATMEL_ID_SPI, &pmc->pcer);

  	if (cs_mask & (1 << 0)) {
  		at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h 
b/arch/arm/include/asm/arch-at91/at91sam9rl.h
index 8eb0d4f..e36282e 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9rl.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9rl.h
@@ -14,35 +14,37 @@
  #ifndef AT91SAM9RL_H
  #define AT91SAM9RL_H

+#define CONFIG_ARM926EJS		/* ARM926EJS Core */
+#define CONFIG_AT91FAMILY		/* it's a member of AT91 */
  /*
   * Peripheral identifiers/interrupts.
   */
-#define AT91_ID_FIQ		0	/* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS		1	/* System Controller */
-#define AT91SAM9RL_ID_PIOA	2	/* Parallel IO Controller A */
-#define AT91SAM9RL_ID_PIOB	3	/* Parallel IO Controller B */
-#define AT91SAM9RL_ID_PIOC	4	/* Parallel IO Controller C */
-#define AT91SAM9RL_ID_PIOD	5	/* Parallel IO Controller D */
-#define AT91SAM9RL_ID_US0	6	/* USART 0 */
-#define AT91SAM9RL_ID_US1	7	/* USART 1 */
-#define AT91SAM9RL_ID_US2	8	/* USART 2 */
-#define AT91SAM9RL_ID_US3	9	/* USART 3 */
-#define AT91SAM9RL_ID_MCI	10	/* Multimedia Card Interface */
-#define AT91SAM9RL_ID_TWI0	11	/* TWI 0 */
-#define AT91SAM9RL_ID_TWI1	12	/* TWI 1 */
-#define AT91SAM9RL_ID_SPI	13	/* Serial Peripheral Interface */
-#define AT91SAM9RL_ID_SSC0	14	/* Serial Synchronous Controller 0 */
-#define AT91SAM9RL_ID_SSC1	15	/* Serial Synchronous Controller 1 */
-#define AT91SAM9RL_ID_TC0	16	/* Timer Counter 0 */
-#define AT91SAM9RL_ID_TC1	17	/* Timer Counter 1 */
-#define AT91SAM9RL_ID_TC2	18	/* Timer Counter 2 */
-#define AT91SAM9RL_ID_PWMC	19	/* Pulse Width Modulation Controller */
-#define AT91SAM9RL_ID_TSC	20	/* Touch Screen Controller */
-#define AT91SAM9RL_ID_DMA	21	/* DMA Controller */
-#define AT91SAM9RL_ID_UDPHS	22	/* USB Device HS */
-#define AT91SAM9RL_ID_LCDC	23	/* LCD Controller */
-#define AT91SAM9RL_ID_AC97C	24	/* AC97 Controller */
-#define AT91SAM9RL_ID_IRQ0	31	/* Advanced Interrupt Controller (IRQ0) */
+#define ATMEL_ID_FIQ		0	/* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS		1	/* System Controller */
+#define ATMEL_ID_PIOA	2	/* Parallel IO Controller A */
+#define ATMEL_ID_PIOB	3	/* Parallel IO Controller B */
+#define ATMEL_ID_PIOC	4	/* Parallel IO Controller C */
+#define ATMEL_ID_PIOD	5	/* Parallel IO Controller D */
+#define ATMEL_ID_US0	6	/* USART 0 */
+#define ATMEL_ID_US1	7	/* USART 1 */
+#define ATMEL_ID_US2	8	/* USART 2 */
+#define ATMEL_ID_US3	9	/* USART 3 */
+#define ATMEL_ID_MCI	10	/* Multimedia Card Interface */
+#define ATMEL_ID_TWI0	11	/* TWI 0 */
+#define ATMEL_ID_TWI1	12	/* TWI 1 */
+#define ATMEL_ID_SPI	13	/* Serial Peripheral Interface */
+#define ATMEL_ID_SSC0	14	/* Serial Synchronous Controller 0 */
+#define ATMEL_ID_SSC1	15	/* Serial Synchronous Controller 1 */
+#define ATMEL_ID_TC0	16	/* Timer Counter 0 */
+#define ATMEL_ID_TC1	17	/* Timer Counter 1 */
+#define ATMEL_ID_TC2	18	/* Timer Counter 2 */
+#define ATMEL_ID_PWMC	19	/* Pulse Width Modulation Controller */
+#define ATMEL_ID_TSC	20	/* Touch Screen Controller */
+#define ATMEL_ID_DMA	21	/* DMA Controller */
+#define ATMEL_ID_UDPHS	22	/* USB Device HS */
+#define ATMEL_ID_LCDC	23	/* LCD Controller */
+#define ATMEL_ID_AC97C	24	/* AC97 Controller */
+#define ATMEL_ID_IRQ0	31	/* Advanced Interrupt Controller (IRQ0) */

  #define AT91_SDRAMC_BASE	0xffffea00
  #define AT91_SMC_BASE		0xffffec00
@@ -53,78 +55,87 @@
  #define AT91_PIT_BASE		0xfffffd30
  #define AT91_WDT_BASE		0xfffffd40

-#ifdef CONFIG_AT91_LEGACY
+//#ifdef CONFIG_AT91_LEGACY

  /*
   * User Peripheral physical base addresses.
   */
-#define AT91SAM9RL_BASE_TCB0	0xfffa0000
-#define AT91SAM9RL_BASE_TC0	0xfffa0000
-#define AT91SAM9RL_BASE_TC1	0xfffa0040
-#define AT91SAM9RL_BASE_TC2	0xfffa0080
-#define AT91SAM9RL_BASE_MCI	0xfffa4000
-#define AT91SAM9RL_BASE_TWI0	0xfffa8000
-#define AT91SAM9RL_BASE_TWI1	0xfffac000
-#define AT91SAM9RL_BASE_US0	0xfffb0000
-#define AT91SAM9RL_BASE_US1	0xfffb4000
-#define AT91SAM9RL_BASE_US2	0xfffb8000
-#define AT91SAM9RL_BASE_US3	0xfffbc000
-#define AT91SAM9RL_BASE_SSC0	0xfffc0000
-#define AT91SAM9RL_BASE_SSC1	0xfffc4000
-#define AT91SAM9RL_BASE_PWMC	0xfffc8000
-#define AT91SAM9RL_BASE_SPI	0xfffcc000
-#define AT91SAM9RL_BASE_TSC	0xfffd0000
-#define AT91SAM9RL_BASE_UDPHS	0xfffd4000
-#define AT91SAM9RL_BASE_AC97C	0xfffd8000
-#define AT91_BASE_SYS		0xffffc000
+#define ATMEL_BASE_TCB0	0xfffa0000
+#define ATMEL_BASE_TC0	0xfffa0000
+#define ATMEL_BASE_TC1	0xfffa0040
+#define ATMEL_BASE_TC2	0xfffa0080
+#define ATMEL_BASE_MCI	0xfffa4000
+#define ATMEL_BASE_TWI0	0xfffa8000
+#define ATMEL_BASE_TWI1	0xfffac000
+#define ATMEL_BASE_US0	0xfffb0000
+#define ATMEL_BASE_US1	0xfffb4000
+#define ATMEL_BASE_US2	0xfffb8000
+#define ATMEL_BASE_US3	0xfffbc000
+#define ATMEL_BASE_SSC0	0xfffc0000
+#define ATMEL_BASE_SSC1	0xfffc4000
+#define ATMEL_BASE_PWMC	0xfffc8000
+#define ATMEL_BASE_SPI	0xfffcc000
+#define ATMEL_BASE_SPI0	0xfffcc000
+#define ATMEL_BASE_TSC	0xfffd0000
+#define ATMEL_BASE_UDPHS	0xfffd4000
+#define ATMEL_BASE_AC97C	0xfffd8000
+#define ATMEL_BASE_SYS		0xffffc000

  /*
   * System Peripherals (offset from AT91_BASE_SYS)
   */
-#define AT91_DMA	(0xffffe600 - AT91_BASE_SYS)
-#define AT91_ECC	(0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC	(0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC	(0xffffec00 - AT91_BASE_SYS)
-#define AT91_MATRIX	(0xffffee00 - AT91_BASE_SYS)
-#define AT91_CCFG	(0xffffef10 - AT91_BASE_SYS)
-#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU	(0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA	(0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB	(0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC	(0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOD	(0xfffffa00 - AT91_BASE_SYS)
-#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC	(0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT	(0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT	(0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT	(0xfffffd40 - AT91_BASE_SYS)
-#define AT91_SCKCR	(0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR	(0xfffffd60 - AT91_BASE_SYS)
-#define AT91_RTC	(0xfffffe00 - AT91_BASE_SYS)
+#define ATMEL_BASE_DMA		0xffffe600
+#define ATMEL_BASE_ECC		0xffffe800
+#define ATMEL_BASE_SDRAMC	0xffffea00
+#define ATMEL_BASE_SMC		0xffffec00
+#define ATMEL_BASE_MATRIX	0xffffee00
+#define ATMEL_BASE_CCFG		0xffffef10
+#define ATMEL_BASE_AIC		0xfffff000
+#define ATMEL_BASE_DBGU		0xfffff200
+#define ATMEL_BASE_PIOA		0xfffff400
+#define ATMEL_BASE_PIOB		0xfffff600
+#define ATMEL_BASE_PIOC		0xfffff800
+#define ATMEL_BASE_PIOD		0xfffffa00
+#define ATMEL_BASE_PMC		0xfffffc00
+#define ATMEL_BASE_RSTC		0xfffffd00
+#define ATMEL_BASE_SHDWC	0xfffffd10
+#define ATMEL_BASE_RTT		0xfffffd20
+#define ATMEL_BASE_PIT		0xfffffd30
+#define ATMEL_BASE_WDT		0xfffffd40
+#define ATMEL_BASE_SCKCR	0xfffffd50
+#define ATMEL_BASE_GPBR		0xfffffd60
+#define ATMEL_BASE_RTC		0xfffffe00

-#define AT91_USART0	AT91SAM9RL_BASE_US0
-#define AT91_USART1	AT91SAM9RL_BASE_US1
-#define AT91_USART2	AT91SAM9RL_BASE_US2
-#define AT91_USART3	AT91SAM9RL_BASE_US3
+#define AT91_USART0	ATMEL_BASE_US0
+#define AT91_USART1	ATMEL_BASE_US1
+#define AT91_USART2	ATMEL_BASE_US2
+#define AT91_USART3	ATMEL_BASE_US3

-#endif /* CONFIG_AT91_LEGACY */
+//#endif /* CONFIG_AT91_LEGACY */

  /*
   * Internal Memory.
   */
-#define AT91SAM9RL_SRAM_BASE	0x00300000	/* Internal SRAM base address */
-#define AT91SAM9RL_SRAM_SIZE	SZ_16K		/* Internal SRAM size (16Kb) */
+#define ATMEL_BASE_SRAM		0x00300000	/* Internal SRAM base address */
+#define ATMEL_SRAM_SIZE		SZ_16K		/* Internal SRAM size (16Kb) */

-#define AT91SAM9RL_ROM_BASE	0x00400000	/* Internal ROM base address */
-#define AT91SAM9RL_ROM_SIZE	(2 * SZ_16K)	/* Internal ROM size (32Kb) */
+#define ATMEL_BASE_ROM		0x00400000	/* Internal ROM base address */
+#define ATMEL_ROM_SIZE		(2 * SZ_16K)	/* Internal ROM size (32Kb) */

  #define AT91SAM9RL_LCDC_BASE	0x00500000	/* LCD Controller */
  #define AT91SAM9RL_UDPHS_BASE	0x00600000	/* USB Device HS controller */

  /*
+ * External memory
+ */
+#define ATMEL_BASE_CS1		0x20000000	/* SDRAM */
+#define ATMEL_BASE_CS3		0x40000000	/* typically NAND */
+
+#define ATMEL_PIO_PORTS		4
+/*
   * Cpu Name
   */
-#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9RL"
+//#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9RL"
+#define ATMEL_CPU_NAME		"AT91SAM9RL"

  #endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h 
b/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
index af8d914..35cde33 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h
@@ -14,83 +14,54 @@
  #ifndef AT91SAM9RL_MATRIX_H
  #define AT91SAM9RL_MATRIX_H

-#define AT91_MATRIX_MCFG0	(AT91_MATRIX + 0x00)	/* Master Configuration 
Register 0 */
-#define AT91_MATRIX_MCFG1	(AT91_MATRIX + 0x04)	/* Master Configuration 
Register 1 */
-#define AT91_MATRIX_MCFG2	(AT91_MATRIX + 0x08)	/* Master Configuration 
Register 2 */
-#define AT91_MATRIX_MCFG3	(AT91_MATRIX + 0x0C)	/* Master Configuration 
Register 3 */
-#define AT91_MATRIX_MCFG4	(AT91_MATRIX + 0x10)	/* Master Configuration 
Register 4 */
-#define AT91_MATRIX_MCFG5	(AT91_MATRIX + 0x14)	/* Master Configuration 
Register 5 */
-#define		AT91_MATRIX_ULBT	(7 << 0)	/* Undefined Length Burst Type */
-#define			AT91_MATRIX_ULBT_INFINITE	(0 << 0)
-#define			AT91_MATRIX_ULBT_SINGLE		(1 << 0)
-#define			AT91_MATRIX_ULBT_FOUR		(2 << 0)
-#define			AT91_MATRIX_ULBT_EIGHT		(3 << 0)
-#define			AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
+#ifndef __ASSEMBLY__

-#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x40)	/* Slave Configuration 
Register 0 */
-#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x44)	/* Slave Configuration 
Register 1 */
-#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x48)	/* Slave Configuration 
Register 2 */
-#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x4C)	/* Slave Configuration 
Register 3 */
-#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x50)	/* Slave Configuration 
Register 4 */
-#define AT91_MATRIX_SCFG5	(AT91_MATRIX + 0x54)	/* Slave Configuration 
Register 5 */
-#define		AT91_MATRIX_SLOT_CYCLE		(0xff << 0)	/* Maximum Number of 
Allowed Cycles for a Burst */
-#define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91_MATRIX_FIXED_DEFMSTR	(0xf  << 18)	/* Fixed Index of 
Default Master */
-#define		AT91_MATRIX_ARBT		(3    << 24)	/* Arbitration Type */
-#define			AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
-#define			AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
+/*
+ * This struct defines access to the matrix' maximum of
+ * 16 masters and 16 slaves.
+ * However, on the AT91SAM9260/9G20/9XE there exist only
+ * 6 Masters and 5 Slaves!
+ */
+struct at91_matrix {
+	u32	mcfg[16];	/* Master Configuration Registers */
+	u32	scfg[16];	/* Slave Configuration Registers */
+	u32	pras[16][2];	/* Priority Assignment Slave Registers */
+	u32	mrcr;		/* Master Remap Control Register */
+	u32	filler[7];
+	u32	ebicsa;		/* EBI Chip Select Assignment Register */
+};
+
+#endif /* __ASSEMBLY__ */

-#define AT91_MATRIX_PRAS0	(AT91_MATRIX + 0x80)	/* Priority Register A 
for Slave 0 */
-#define AT91_MATRIX_PRAS1	(AT91_MATRIX + 0x88)	/* Priority Register A 
for Slave 1 */
-#define AT91_MATRIX_PRAS2	(AT91_MATRIX + 0x90)	/* Priority Register A 
for Slave 2 */
-#define AT91_MATRIX_PRAS3	(AT91_MATRIX + 0x98)	/* Priority Register A 
for Slave 3 */
-#define AT91_MATRIX_PRAS4	(AT91_MATRIX + 0xA0)	/* Priority Register A 
for Slave 4 */
-#define AT91_MATRIX_PRAS5	(AT91_MATRIX + 0xA8)	/* Priority Register A 
for Slave 5 */
-#define		AT91_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
-#define		AT91_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
-#define		AT91_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
-#define		AT91_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
-#define		AT91_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
-#define		AT91_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
+#define AT91_MATRIX_ULBT_INFINITE	(0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE		(1 << 0)
+#define AT91_MATRIX_ULBT_FOUR		(2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT		(3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)

-#define AT91_MATRIX_MRCR	(AT91_MATRIX + 0x100)	/* Master Remap Control 
Register */
-#define		AT91_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 
(ARM926EJ-S Instruction Master) */
-#define		AT91_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 
(ARM926EJ-S Data Master) */
-#define		AT91_MATRIX_RCB2		(1 << 2)
-#define		AT91_MATRIX_RCB3		(1 << 3)
-#define		AT91_MATRIX_RCB4		(1 << 4)
-#define		AT91_MATRIX_RCB5		(1 << 5)
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT	18
+#define AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)

-#define AT91_MATRIX_TCMR	(AT91_MATRIX + 0x114)	/* TCM Configuration 
Register */
-#define		AT91_MATRIX_ITCM_SIZE		(0xf << 0)	/* Size of ITCM enabled 
memory block */
-#define			AT91_MATRIX_ITCM_0		(0 << 0)
-#define			AT91_MATRIX_ITCM_16		(5 << 0)
-#define			AT91_MATRIX_ITCM_32		(6 << 0)
-#define		AT91_MATRIX_DTCM_SIZE		(0xf << 4)	/* Size of DTCM enabled 
memory block */
-#define			AT91_MATRIX_DTCM_0		(0 << 4)
-#define			AT91_MATRIX_DTCM_16		(5 << 4)
-#define			AT91_MATRIX_DTCM_32		(6 << 4)
+#define AT91_MATRIX_M0PR_SHIFT		0
+#define AT91_MATRIX_M1PR_SHIFT		4
+#define AT91_MATRIX_M2PR_SHIFT		8
+#define AT91_MATRIX_M3PR_SHIFT		12
+#define AT91_MATRIX_M4PR_SHIFT		16
+#define AT91_MATRIX_M5PR_SHIFT		20

-#define AT91_MATRIX_EBICSA	(AT91_MATRIX + 0x120)	/* EBI0 Chip Select 
Assignment Register */
-#define		AT91_MATRIX_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91_MATRIX_CS1A_SMC		(0 << 1)
-#define			AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
-#define		AT91_MATRIX_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91_MATRIX_CS3A_SMC		(0 << 3)
-#define			AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91_MATRIX_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
-#define			AT91_MATRIX_CS4A_SMC		(0 << 4)
-#define			AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
-#define		AT91_MATRIX_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
-#define			AT91_MATRIX_CS5A_SMC		(0 << 5)
-#define			AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
-#define		AT91_MATRIX_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define		AT91_MATRIX_VDDIOMSEL		(1 << 16)	/* Memory voltage selection */
-#define			AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
-#define			AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
+#define AT91_MATRIX_RCB0		(1 << 0)
+#define AT91_MATRIX_RCB1		(1 << 1)

+#define AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
+#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
+#define AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
+#define AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
+#define AT91_MATRIX_DBPUC		(1 << 8)
+#define AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)

  #endif
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c 
b/board/atmel/at91sam9rlek/at91sam9rlek.c
index e374917..9e5449a 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -23,6 +23,7 @@
   */

  #include <common.h>
+#include <asm/io.h>
  #include <asm/arch/at91sam9rl.h>
  #include <asm/arch/at91sam9rl_matrix.h>
  #include <asm/arch/at91sam9_smc.h>
@@ -31,7 +32,7 @@
  #include <asm/arch/at91_rstc.h>
  #include <asm/arch/clk.h>
  #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+
  #include <lcd.h>
  #include <atmel_lcdc.h>
  #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
@@ -48,33 +49,37 @@ DECLARE_GLOBAL_DATA_PTR;
  #ifdef CONFIG_CMD_NAND
  static void at91sam9rlek_nand_hw_init(void)
  {
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  	unsigned long csa;

  	/* Enable CS3 */
-	csa = at91_sys_read(AT91_MATRIX_EBICSA);
-	at91_sys_write(AT91_MATRIX_EBICSA,
-		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+
+	writel(csa, &matrix->ebicsa);

  	/* Configure SMC CS3 for NAND/SmartMedia */
-	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(3),
-		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-	at91_sys_write(AT91_SMC_CYCLE(3),
-		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
-	at91_sys_write(AT91_SMC_MODE(3),
-		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		       AT91_SMC_EXNWMODE_DISABLE |
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+		&smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+		&smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
  #ifdef CONFIG_SYS_NAND_DBW_16
-		       AT91_SMC_DBW_16 |
+		AT91_SMC_MODE_DBW_16 |
  #else /* CONFIG_SYS_NAND_DBW_8 */
-		       AT91_SMC_DBW_8 |
+		AT91_SMC_MODE_DBW_8 |
  #endif
-		       AT91_SMC_TDF_(2));
+		AT91_SMC_MODE_TDF_CYCLE(2),
+		&smc->cs[3].mode);

-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
+	writel(1 << ATMEL_ID_PIOD, &pmc->pcer);

  	/* Configure RDY/BSY */
  	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -116,6 +121,8 @@ void lcd_disable(void)
  }
  static void at91sam9rlek_lcd_hw_init(void)
  {
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
  	at91_set_B_periph(AT91_PIN_PC1, 0);	/* LCDPWR */
  	at91_set_A_periph(AT91_PIN_PC5, 0);	/* LCDHSYNC */
  	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDDOTCK */
@@ -138,9 +145,9 @@ static void at91sam9rlek_lcd_hw_init(void)
  	at91_set_B_periph(AT91_PIN_PC24, 0);	/* LCDD22 */
  	at91_set_B_periph(AT91_PIN_PC25, 0);	/* LCDD23 */

-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC);
+	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);

-	gd->fb_base = 0;
+	gd->fb_base = CONFIG_FB_ADDR;
  }

  #ifdef CONFIG_LCD_INFO
@@ -157,7 +164,7 @@ void lcd_show_board_info(void)
  	lcd_printf ("(C) 2008 ATMEL Corp\n");
  	lcd_printf ("at91support@atmel.com\n");
  	lcd_printf ("%s CPU at %s MHz\n",
-		CONFIG_SYS_AT91_CPU_NAME,
+		ATMEL_CPU_NAME,
  		strmhz(temp, get_cpu_clk_rate()));

  	dram_size = 0;
@@ -173,6 +180,17 @@ void lcd_show_board_info(void)
  #endif /* CONFIG_LCD_INFO */
  #endif

+int board_early_init_f(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable clocks for all PIOs */
+	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+		(1 << ATMEL_ID_PIOC) | (1 << ATMEL_ID_PIOD),
+		&pmc->pcer);
+
+	return 0;
+}

  int board_init(void)
  {
@@ -182,7 +200,7 @@ int board_init(void)
  	/* arch number of AT91SAM9RLEK-Board */
  	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
  	/* adress of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

  	at91_serial_hw_init();
  #ifdef CONFIG_CMD_NAND
@@ -199,7 +217,8 @@ int board_init(void)

  int dram_init(void)
  {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	gd->ram_size = get_ram_size(
+		(void *)CONFIG_SYS_SDRAM_BASE,
+		CONFIG_SYS_SDRAM_SIZE);
  	return 0;
  }
diff --git a/board/atmel/at91sam9rlek/config.mk 
b/board/atmel/at91sam9rlek/config.mk
deleted file mode 100644
index e554a45..0000000
--- a/board/atmel/at91sam9rlek/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x23f00000
diff --git a/board/atmel/at91sam9rlek/led.c b/board/atmel/at91sam9rlek/led.c
index 9634cc0..987e8c0 100644
--- a/board/atmel/at91sam9rlek/led.c
+++ b/board/atmel/at91sam9rlek/led.c
@@ -26,12 +26,14 @@
  #include <asm/arch/at91sam9rl.h>
  #include <asm/arch/at91_pmc.h>
  #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+#include <asm/io.h>

  void coloured_LED_init(void)
  {
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
  	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
+	writel(ATMEL_ID_PIOD, &pmc->pcer);

  	at91_set_gpio_output(CONFIG_RED_LED, 1);
  	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
diff --git a/boards.cfg b/boards.cfg
index ac20c81..561bafd 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -83,6 +83,9 @@ at91sam9g20ek_dataflash_cs1  arm         arm926ejs 
at91sam9260ek       atmel
  at91sam9xeek_nandflash       arm         arm926ejs   at91sam9260ek 
    atmel          at91        at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH
  at91sam9xeek_dataflash_cs0   arm         arm926ejs   at91sam9260ek 
    atmel          at91 
at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0
  at91sam9xeek_dataflash_cs1   arm         arm926ejs   at91sam9260ek 
    atmel          at91 
at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1
+at91sam9rlek_nandflash       arm         arm926ejs   at91sam9rlek 
   atmel          at91        at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH
+at91sam9rlek_dataflash_cs0   arm         arm926ejs   at91sam9rlek 
   atmel          at91        at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH_CS0
+at91sam9rlek_dataflash       arm         arm926ejs   at91sam9rlek 
   atmel          at91        at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH_CS0
  snapper9260                  arm         arm926ejs   - 
    bluewater      at91        snapper9260:AT91SAM9260
  snapper9g20                  arm         arm926ejs   snapper9260 
    bluewater      at91        snapper9260:AT91SAM9G20
  cpu9260                      arm         arm926ejs   cpu9260 
    eukrea         at91        cpu9260:CPU9260
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 8dbd082..8b69f6e 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -27,33 +27,43 @@
  #ifndef __CONFIG_H
  #define __CONFIG_H

-#define CONFIG_AT91_LEGACY
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE	0x21f00000

  /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
-#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* main clock xtal */
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_AT91SAM9RLEK	1	/* It's an AT91SAM9RLEK Board	*/

-#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
-#define CONFIG_AT91SAM9RL	1	/* It's an Atmel AT91SAM9RL SoC*/
-#define CONFIG_AT91SAM9RLEK	1	/* on an AT91SAM9RLEK Board	*/
  #define CONFIG_ARCH_CPU_INIT
  #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/

-#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	1
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1

  #define CONFIG_SKIP_LOWLEVEL_INIT

+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_AT91_GPIO		1
+#define CONFIG_AT91_GPIO_PULLUP		1
+
  /*
   * Hardware drivers
   */
-#define CONFIG_AT91_GPIO	1
-#define CONFIG_ATMEL_USART	1
-#undef CONFIG_USART0
-#undef CONFIG_USART1
-#undef CONFIG_USART2
-#define CONFIG_USART3		1	/* USART 3 is DBGU */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}

  /* LCD */
  #define CONFIG_LCD			1
@@ -62,10 +72,12 @@
  #undef LCD_TEST_PATTERN
  #define CONFIG_LCD_INFO			1
  #define CONFIG_LCD_INFO_BELOW_LOGO	1
-#define CONFIG_SYS_WHITE_ON_BLACK		1
+#define CONFIG_SYS_WHITE_ON_BLACK	1
  #define CONFIG_ATMEL_LCD		1
  #define CONFIG_ATMEL_LCD_RGB565		1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
+#define CONFIG_FB_ADDR			0x23600000
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+

  /* LED */
  #define CONFIG_AT91_LED
@@ -85,6 +97,7 @@
  #undef CONFIG_CMD_IMLS
  #undef CONFIG_CMD_LOADS
  #undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
  #undef CONFIG_CMD_SOURCE
  #undef CONFIG_CMD_USB

@@ -92,8 +105,15 @@

  /* SDRAM */
  #define CONFIG_NR_DRAM_BANKS		1
+#if 0
  #define PHYS_SDRAM			0x20000000
  #define PHYS_SDRAM_SIZE			0x04000000	/* 64 megs */
+#endif
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)

  /* DataFlash */
  #define CONFIG_ATMEL_DATAFLASH_SPI
@@ -112,7 +132,7 @@
  #ifdef CONFIG_CMD_NAND
  #define CONFIG_NAND_ATMEL
  #define CONFIG_SYS_MAX_NAND_DEVICE		1
-#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
  #define CONFIG_SYS_NAND_DBW_8			1
  /* our ALE is AD21 */
  #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
@@ -129,7 +149,7 @@

  #define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */

-#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
  #define CONFIG_SYS_MEMTEST_END			0x23e00000

  #ifdef CONFIG_SYS_USE_DATAFLASH
@@ -161,9 +181,6 @@

  #endif

-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
-
  #define CONFIG_SYS_PROMPT		"U-Boot> "
  #define CONFIG_SYS_CBSIZE		256
  #define CONFIG_SYS_MAXARGS		16
@@ -178,8 +195,6 @@

  #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */

-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
+#undef CONFIG_USE_IRQ

  #endif
