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Wed, 31 Aug 2022 19:04:36 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 31 Aug 2022 19:04:35 +0800 Received: from mcddlt001.gcn.mediatek.inc (10.19.240.15) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 31 Aug 2022 19:04:34 +0800 From: Weijie Gao To: CC: GSS_MTK_Uboot_upstream , Weijie Gao Subject: [PATCH v2 11/32] arm: dts: mt7622: force high-speed mode for uart Date: Wed, 31 Aug 2022 19:04:34 +0800 Message-ID: <485c39decebd661a15e9fcd19e64557fcf000ef6.1661941661.git.weijie.gao@mediatek.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: References: MIME-Version: 1.0 X-MTK: N X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean The input clock for uart is too slow (25MHz) which introduces frequent data error on both receiving and transmitting even if the baudrate is 115200. Using high-speed can significantly solve this issue. Reviewed-by: Simon Glass Signed-off-by: Weijie Gao Tested-by: Daniel Golle --- v2 changes: none --- arch/arm/dts/mt7622.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index 0127474c95..fb6c1b7154 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -175,6 +175,7 @@ status = "disabled"; assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; + mediatek,force-highspeed; }; mmc0: mmc@11230000 {