Message ID | 485c39decebd661a15e9fcd19e64557fcf000ef6.1661941661.git.weijie.gao@mediatek.com |
---|---|
State | Superseded |
Delegated to: | Tom Rini |
Headers | show |
Series | Add support for MediaTek MT7981/MT7986 SoCs - v2 | expand |
On Wed, Aug 31, 2022 at 07:04:34PM +0800, Weijie Gao wrote: > The input clock for uart is too slow (25MHz) which introduces frequent data > error on both receiving and transmitting even if the baudrate is 115200. > > Using high-speed can significantly solve this issue. Tested on Bananapi BPi-R64 (MT7622). Fixes unstable console issues previously observed on MT7622 systems. Tested-by: Daniel Golle <daniel@makrotopia.org> > > Reviewed-by: Simon Glass <sjg@chromium.org> > Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> > --- > v2 changes: none > --- > arch/arm/dts/mt7622.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi > index 0127474c95..fb6c1b7154 100644 > --- a/arch/arm/dts/mt7622.dtsi > +++ b/arch/arm/dts/mt7622.dtsi > @@ -175,6 +175,7 @@ > status = "disabled"; > assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; > assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; > + mediatek,force-highspeed; > }; > > mmc0: mmc@11230000 { > -- > 2.17.1 >
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index 0127474c95..fb6c1b7154 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -175,6 +175,7 @@ status = "disabled"; assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; + mediatek,force-highspeed; }; mmc0: mmc@11230000 {