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Mon, 11 Mar 2024 12:23:11 -0500 From: Tejas Bhumkar To: CC: , , , , , Ashok Reddy Soma Subject: [PATCH 06/19] spi: cadence_qspi: Initialize read and write watermark registers Date: Mon, 11 Mar 2024 22:52:36 +0530 Message-ID: <3c2f5ec9cb90b50b5c6c6ae960dd0e062d62dd58.1710098033.git.tejas.arvind.bhumkar@amd.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: tejas.arvind.bhumkar@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343E:EE_|LV8PR12MB9451:EE_ X-MS-Office365-Filtering-Correlation-Id: bd045210-4afe-4ccc-9a4d-08dc41efef32 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sFeBlMJdGrMGy2u0OAIZtpRf88SC6qNkeHBFxr07YLCtWYg6sJ6H6OrCT2l7UOqpOOF3w6HuM2Vw7uJokGfk1VOESSe0O3aMPp+0YNkWFoghWtJP9ykMig7DuYpd8JDZe4/Y4dznNtt5EXSBMYCBZQb+sz+c2Wb2SIQK6k/MUwzn3CbaQeR5lWRSHI2CtGwKaL/pX2peUEMnNNcY5nCcD/orW68rmchYgF1HxEBg1jnS9kv7yWfCRyuugtsrpvVOM7x6KbiDX2fxRWrBgdTapUyw0Xzf/rVBE3/flZEq6yeBwUsOSAOuJGmhlDw4Jw6EB22ycDOMWBgdhimWtKKx0u5BIFxgc4unK/bVgZZf4DKyJQVoZu4TDi8NfT9VqqpgJPhhHTUoVPZp4AMKAM8Q6ekWFcptvfTmDFcBhInbhTX3rbEf65oUOG0XaC4tiAVT/FXgPOsCsuJtLUihYSOoo3up/aeJvtQmrIOPgYQYEOS+zEJKFWZEHNtHSmopDF1mbZ4iv0GEkCc6SDnMzh8R4IosBDZUD8optGVPawobYBPfp8I2x2HvnQV8IVzRnFZOBj8jQX21lXuPZTwc4ie6d6hssWN1q7Pe5uzThx7XGDFx8t3o+sQj6RRl4eP62rNsBgHn8ClTdSB91itZqDWNEcd8bAolG5sj0HG7PRtXpjCUR52VSRKYs6wySY0sz7Zu/rVe5n210dOhHiRBS36Kr8mUuB7r9KKg5U+glhM1mehW8UV7TtpQ7Rcoej7j+5Vs X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(82310400014)(36860700004)(1800799015)(376005); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Mar 2024 17:23:14.5046 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd045210-4afe-4ccc-9a4d-08dc41efef32 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9451 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Ashok Reddy Soma Read and Write watermark registers are not initialized. Set read watermark to half of the FIFO and write watermark to 1/8 of the FIFO size. Read watermark indicates if SRAM fill level is above this watermark, interrupt will be generated and read or DMA can be performed. Write watermark indicates the maximum fill level of SRAM when write is performed to device. These values of 1/2 for read and 1/8 for write are chosen similar to Linux driver. Signed-off-by: Ashok Reddy Soma Signed-off-by: Tejas Bhumkar --- drivers/spi/cadence_qspi_apb.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 35a21a2727..8ea40551c1 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -356,6 +356,14 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_priv *priv) /* Indirect mode configurations */ writel(priv->fifo_depth / 2, priv->regbase + CQSPI_REG_SRAMPARTITION); + /* Program read watermark -- 1/2 of the FIFO. */ + writel(priv->fifo_depth * priv->fifo_width / 2, + priv->regbase + CQSPI_REG_INDIRECTRDWATERMARK); + + /* Program write watermark -- 1/8 of the FIFO. */ + writel(priv->fifo_depth * priv->fifo_width / 8, + priv->regbase + CQSPI_REG_INDIRECTWRWATERMARK); + /* Disable all interrupts */ writel(0, priv->regbase + CQSPI_REG_IRQMASK);