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[06/19] spi: cadence_qspi: Initialize read and write watermark registers

Message ID 3c2f5ec9cb90b50b5c6c6ae960dd0e062d62dd58.1710098033.git.tejas.arvind.bhumkar@amd.com
State Deferred
Delegated to: Tom Rini
Headers show
Series Add support for DDR PHY mode | expand

Commit Message

Bhumkar, Tejas Arvind March 11, 2024, 5:22 p.m. UTC 
From: Ashok Reddy Soma <ashok.reddy.soma@amd.com>

Read and Write watermark registers are not initialized. Set read
watermark to half of the FIFO and write watermark to 1/8 of the
FIFO size.

Read watermark indicates if SRAM fill level is above this watermark,
interrupt will be generated and read or DMA can be performed.

Write watermark indicates the maximum fill level of SRAM when write is
performed to device.

These values of 1/2 for read and 1/8 for write are chosen similar to
Linux driver.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
---
 drivers/spi/cadence_qspi_apb.c | 8 ++++++++
 1 file changed, 8 insertions(+)
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Patch

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 35a21a2727..8ea40551c1 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -356,6 +356,14 @@  void cadence_qspi_apb_controller_init(struct cadence_spi_priv *priv)
 	/* Indirect mode configurations */
 	writel(priv->fifo_depth / 2, priv->regbase + CQSPI_REG_SRAMPARTITION);
 
+	/* Program read watermark -- 1/2 of the FIFO. */
+	writel(priv->fifo_depth * priv->fifo_width / 2,
+	       priv->regbase + CQSPI_REG_INDIRECTRDWATERMARK);
+
+	/* Program write watermark -- 1/8 of the FIFO. */
+	writel(priv->fifo_depth * priv->fifo_width / 8,
+	       priv->regbase + CQSPI_REG_INDIRECTWRWATERMARK);
+
 	/* Disable all interrupts */
 	writel(0, priv->regbase + CQSPI_REG_IRQMASK);