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Mon, 10 May 2021 07:17:59 -0700 (PDT) From: Michal Simek To: u-boot@lists.denx.de, git@xilinx.com Cc: Saeed Nowshadi Subject: [PATCH 02/10] arm64: zynqmp: Add 'silabs, skip-recall' to DDR DIMM si570 clk node Date: Mon, 10 May 2021 16:17:41 +0200 Message-Id: <306b9a16b1f29b85ad22079529205c6ba5628707.1620656248.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: Saeed Nowshadi The 'silabs,skip-recall' property prevents interruption in operation of the clock while the driver is being probed. Without this property, the DDR DIMM clk can cause a failure during Versal's boot. Signed-off-by: Saeed Nowshadi Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 135c83f502e8..e5d75e552346 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019 - 2020, Xilinx, Inc. + * (C) Copyright 2019 - 2021, Xilinx, Inc. * * Michal Simek */ @@ -505,6 +505,7 @@ factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; + silabs,skip-recall; }; }; i2c@4 { /* LPDDR4_SI570_CLK2 */