diff mbox series

[11/31] arm: dts: mt7622: force high-speed mode for uart

Message ID 28cb1144baf6af98952b671f53005a2c7dcad071.1659581119.git.weijie.gao@mediatek.com
State Superseded
Delegated to: Tom Rini
Headers show
Series Add support for MediaTek MT7981/MT7986 SoCs | expand

Commit Message

Weijie Gao (高惟杰) Aug. 4, 2022, 3:35 a.m. UTC 
The input clock for uart is too slow (25MHz) which introduces frequent data
error on both receiving and transmitting even if the baudrate is 115200.

Using high-speed can significantly solve this issue.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
 arch/arm/dts/mt7622.dtsi | 1 +
 1 file changed, 1 insertion(+)

Comments

Simon Glass Aug. 4, 2022, 1:57 p.m. UTC | #1 
On Wed, 3 Aug 2022 at 21:37, Weijie Gao <weijie.gao@mediatek.com> wrote:
>
> The input clock for uart is too slow (25MHz) which introduces frequent data
> error on both receiving and transmitting even if the baudrate is 115200.
>
> Using high-speed can significantly solve this issue.
>
> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
> ---
>  arch/arm/dts/mt7622.dtsi | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Simon Glass <sjg@chromium.org>
diff mbox series

Patch

diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index 0127474c95..fb6c1b7154 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -175,6 +175,7 @@ 
 		status = "disabled";
 		assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 		assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
+		mediatek,force-highspeed;
 	};
 
 	mmc0: mmc@11230000 {