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Wed, 29 May 2024 14:48:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MN1PEPF0000ECDB.mail.protection.outlook.com (10.167.242.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7633.15 via Frontend Transport; Wed, 29 May 2024 14:48:16 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 29 May 2024 09:48:15 -0500 From: Michal Simek To: , CC: Chanho Park , Minkyu Kang , Sam Protsenko , "Simon Glass" , Tejas Bhumkar , "Tom Rini" , Venkatesh Yadav Abbarapu Subject: [PATCH 2/4] soc: versal2: Add SoC driver for AMD Versal Gen 2 Date: Wed, 29 May 2024 16:47:59 +0200 Message-ID: <22cf9c765e47ab03dbf2b8363e6626e809113432.1716994063.git.michal.simek@amd.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; 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Also enable it via defconfig. Signed-off-by: Michal Simek --- configs/amd_versal2_virt_defconfig | 1 + drivers/soc/Kconfig | 8 ++++ drivers/soc/Makefile | 1 + drivers/soc/soc_amd_versal2.c | 77 ++++++++++++++++++++++++++++++ 4 files changed, 87 insertions(+) create mode 100644 drivers/soc/soc_amd_versal2.c diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 5eea07f03f51..8ef86f1f3830 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -119,6 +119,7 @@ CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y CONFIG_XILINX_UARTLITE=y CONFIG_SOC_DEVICE=y +CONFIG_SOC_AMD_VERSAL2=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_ZYNQ_SPI=y diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 03433bc0e6d2..cee506fe4747 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -9,6 +9,14 @@ config SOC_DEVICE need different parameters or quirks enabled depending on the specific device variant in use. +config SOC_AMD_VERSAL2 + bool "Enable SoC Device ID driver for AMD Versal Gen 2" + depends on SOC_DEVICE && ARCH_VERSAL2 + help + Enable this option to select SoC device id driver for AMD Versal Gen 2. + This allows other drivers to verify the SoC familiy & revision using + matching SoC attributes. + config SOC_DEVICE_TI_K3 depends on SOC_DEVICE && ARCH_K3 bool "Enable SoC Device ID driver for TI K3 SoCs" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 610bf816d40a..5ec89a053165 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -2,6 +2,7 @@ # # Makefile for the U-Boot SOC specific device drivers. +obj-$(CONFIG_SOC_AMD_VERSAL2) += soc_amd_versal2.o obj-$(CONFIG_SOC_SAMSUNG) += samsung/ obj-$(CONFIG_SOC_TI) += ti/ obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o diff --git a/drivers/soc/soc_amd_versal2.c b/drivers/soc/soc_amd_versal2.c new file mode 100644 index 000000000000..66bcb22b4fa9 --- /dev/null +++ b/drivers/soc/soc_amd_versal2.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD Versal Gen 2 SOC driver + * + * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include + +#include + +/* + * v1 -> 0x10 - ES1 + * v2 -> 0x20 - Production + */ +static const char versal2_family[] = "Versal Gen 2"; + +struct soc_amd_versal2_priv { + const char *family; + char revision; +}; + +static int soc_amd_versal2_get_family(struct udevice *dev, char *buf, int size) +{ + struct soc_amd_versal2_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "%s", priv->family); +} + +static int soc_amd_versal2_get_revision(struct udevice *dev, char *buf, int size) +{ + struct soc_amd_versal2_priv *priv = dev_get_priv(dev); + + return snprintf(buf, size, "v%d", priv->revision); +} + +static const struct soc_ops soc_amd_versal2_ops = { + .get_family = soc_amd_versal2_get_family, + .get_revision = soc_amd_versal2_get_revision, +}; + +static int soc_amd_versal2_probe(struct udevice *dev) +{ + struct soc_amd_versal2_priv *priv = dev_get_priv(dev); + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + priv->family = versal2_family; + + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) { + ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, + ret_payload); + if (ret) + return ret; + } else { + ret_payload[2] = readl(PMC_TAP_VERSION); + if (!ret_payload[2]) + return -EINVAL; + } + + priv->revision = FIELD_GET(PS_VERSION_MASK, ret_payload[2]); + + return 0; +} + +U_BOOT_DRIVER(soc_amd_versal2) = { + .name = "soc_amd_versal2", + .id = UCLASS_SOC, + .ops = &soc_amd_versal2_ops, + .probe = soc_amd_versal2_probe, + .priv_auto = sizeof(struct soc_amd_versal2_priv), + .flags = DM_FLAG_PRE_RELOC, +};