diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
index c67c3cf..9b083c0 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
@@ -110,10 +110,11 @@ void enable_usboh3_clk(unsigned char enable)
 	unsigned int reg;
 
 	reg = readl(&mxc_ccm->CCGR2);
+	reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR2_USBOH3_60M_OFFSET);
 	if (enable)
-		reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
+		reg |= MXC_CCM_CCGR_CG_ON << MXC_CCM_CCGR2_USBOH3_60M_OFFSET;
 	else
-		reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
+		reg |= MXC_CCM_CCGR_CG_OFF << MXC_CCM_CCGR2_USBOH3_60M_OFFSET;
 	writel(reg, &mxc_ccm->CCGR2);
 }
 
@@ -137,6 +138,29 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 }
 #endif
 
+#if defined(CONFIG_MX51)
+void set_usb_phy_clk(void)
+{
+	unsigned int reg;
+
+	reg = readl(&mxc_ccm->cscmr1);
+	reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
+	writel(reg, &mxc_ccm->cscmr1);
+}
+
+void enable_usb_phy_clk(unsigned char enable)
+{
+	unsigned int reg;
+
+	reg = readl(&mxc_ccm->CCGR2);
+	reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR2_USB_PHY_OFFSET);
+	if (enable)
+		reg |= MXC_CCM_CCGR_CG_ON << MXC_CCM_CCGR2_USB_PHY_OFFSET;
+	else
+		reg |= MXC_CCM_CCGR_CG_OFF << MXC_CCM_CCGR2_USB_PHY_OFFSET;
+	writel(reg, &mxc_ccm->CCGR2);
+}
+#elif defined(CONFIG_MX53)
 void set_usb_phy1_clk(void)
 {
 	unsigned int reg;
@@ -151,10 +175,11 @@ void enable_usb_phy1_clk(unsigned char enable)
 	unsigned int reg;
 
 	reg = readl(&mxc_ccm->CCGR4);
+	reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR4_USB_PHY1_OFFSET);
 	if (enable)
-		reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET;
+		reg |= MXC_CCM_CCGR_CG_ON << MXC_CCM_CCGR4_USB_PHY1_OFFSET;
 	else
-		reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET);
+		reg |= MXC_CCM_CCGR_CG_OFF << MXC_CCM_CCGR4_USB_PHY1_OFFSET;
 	writel(reg, &mxc_ccm->CCGR4);
 }
 
@@ -172,12 +197,14 @@ void enable_usb_phy2_clk(unsigned char enable)
 	unsigned int reg;
 
 	reg = readl(&mxc_ccm->CCGR4);
+	reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR4_USB_PHY2_OFFSET);
 	if (enable)
-		reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET;
+		reg |= MXC_CCM_CCGR_CG_ON << MXC_CCM_CCGR4_USB_PHY2_OFFSET;
 	else
-		reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET);
+		reg |= MXC_CCM_CCGR_CG_OFF << MXC_CCM_CCGR4_USB_PHY2_OFFSET;
 	writel(reg, &mxc_ccm->CCGR4);
 }
+#endif
 
 /*
  * Calculate the frequency of PLLn.
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/clock.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/clock.h
index 8d8fa18..a03e61a 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/clock.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/clock.h
@@ -42,8 +42,15 @@ u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
 int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
+#if defined(CONFIG_MX51)
+void set_usb_phy_clk(void);
+void enable_usb_phy_clk(unsigned char enable);
+#elif defined(CONFIG_MX53)
+void set_usb_phy1_clk(void);
+void enable_usb_phy1_clk(unsigned char enable);
 void set_usb_phy2_clk(void);
 void enable_usb_phy2_clk(unsigned char enable);
+#endif
 void set_usboh3_clk(void);
 void enable_usboh3_clk(unsigned char enable);
 void mxc_set_sata_internal_clock(void);
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/crm_regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/crm_regs.h
index 4e0fc1b..4fd8dba 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -200,11 +200,161 @@ struct mxc_ccm_reg {
 
 /* Define the bits in register CCGRx */
 #define MXC_CCM_CCGR_CG_MASK				0x3
+#define MXC_CCM_CCGR_CG_OFF				0x0
+#define MXC_CCM_CCGR_CG_RUN_ON				0x1
+#define MXC_CCM_CCGR_CG_ON				0x3
 
-#define MXC_CCM_CCGR4_CG5_OFFSET			10
-#define MXC_CCM_CCGR4_CG6_OFFSET			12
-#define MXC_CCM_CCGR5_CG5_OFFSET			10
-#define MXC_CCM_CCGR2_CG14_OFFSET			28
+#define MXC_CCM_CCGR0_ARM_BUS_OFFSET			0
+#define MXC_CCM_CCGR0_ARM_AXI_OFFSET			2
+#define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET			4
+#define MXC_CCM_CCGR0_TZIC_OFFSET			6
+#define MXC_CCM_CCGR0_DAP_OFFSET			8
+#define MXC_CCM_CCGR0_TPIU_OFFSET			10
+#define MXC_CCM_CCGR0_CTI2_OFFSET			12
+#define MXC_CCM_CCGR0_CTI3_OFFSET			14
+#define MXC_CCM_CCGR0_AHBMUX1_OFFSET			16
+#define MXC_CCM_CCGR0_AHBMUX2_OFFSET			18
+#define MXC_CCM_CCGR0_ROMCP_OFFSET			20
+#define MXC_CCM_CCGR0_ROM_OFFSET			22
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET			24
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET			26
+#define MXC_CCM_CCGR0_AHB_MAX_OFFSET			28
+#define MXC_CCM_CCGR0_IIM_OFFSET			30
+
+#define MXC_CCM_CCGR1_TMAX1_OFFSET			0
+#define MXC_CCM_CCGR1_TMAX2_OFFSET			2
+#define MXC_CCM_CCGR1_TMAX3_OFFSET			4
+#define MXC_CCM_CCGR1_UART1_IPG_OFFSET			6
+#define MXC_CCM_CCGR1_UART1_PER_OFFSET			8
+#define MXC_CCM_CCGR1_UART2_IPG_OFFSET			10
+#define MXC_CCM_CCGR1_UART2_PER_OFFSET			12
+#define MXC_CCM_CCGR1_UART3_IPG_OFFSET			14
+#define MXC_CCM_CCGR1_UART3_PER_OFFSET			16
+#define MXC_CCM_CCGR1_I2C1_OFFSET			18
+#define MXC_CCM_CCGR1_I2C2_OFFSET			20
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET			22
+#define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET		24
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR1_I2C3_OFFSET			22
+#endif
+#define MXC_CCM_CCGR1_FIRI_IPG_OFFSET			26
+#define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET		28
+#define MXC_CCM_CCGR1_SCC_OFFSET			30
+
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR2_USB_PHY_OFFSET			0
+#endif
+#define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET			2
+#define MXC_CCM_CCGR2_EPIT1_HF_OFFSET			4
+#define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET			6
+#define MXC_CCM_CCGR2_EPIT2_HF_OFFSET			8
+#define MXC_CCM_CCGR2_PWM1_IPG_OFFSET			10
+#define MXC_CCM_CCGR2_PWM1_HF_OFFSET			12
+#define MXC_CCM_CCGR2_PWM2_IPG_OFFSET			14
+#define MXC_CCM_CCGR2_PWM2_HF_OFFSET			16
+#define MXC_CCM_CCGR2_GPT_IPG_OFFSET			18
+#define MXC_CCM_CCGR2_GPT_HF_OFFSET			20
+#define MXC_CCM_CCGR2_OWIRE_OFFSET			22
+#define MXC_CCM_CCGR2_FEC_OFFSET			24
+#define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET		26
+#define MXC_CCM_CCGR2_USBOH3_60M_OFFSET			28
+#define MXC_CCM_CCGR2_TVE_OFFSET			30
+
+#define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET			0
+#define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET			2
+#define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET			4
+#define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET			6
+#define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET			8
+#define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET			10
+#define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET			12
+#define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET			14
+#define MXC_CCM_CCGR3_SSI1_IPG_OFFSET			16
+#define MXC_CCM_CCGR3_SSI1_SSI_OFFSET			18
+#define MXC_CCM_CCGR3_SSI2_IPG_OFFSET			20
+#define MXC_CCM_CCGR3_SSI2_SSI_OFFSET			22
+#define MXC_CCM_CCGR3_SSI3_IPG_OFFSET			24
+#define MXC_CCM_CCGR3_SSI3_SSI_OFFSET			26
+#define MXC_CCM_CCGR3_SSI_EXT1_OFFSET			28
+#define MXC_CCM_CCGR3_SSI_EXT2_OFFSET			30
+
+#define MXC_CCM_CCGR4_PATA_OFFSET			0
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR4_SIM_IPG_OFFSET			2
+#define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET			4
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR4_SATA_OFFSET			2
+#define MXC_CCM_CCGR4_CAN2_IPG_OFFSET			6
+#define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET		8
+#define MXC_CCM_CCGR4_USB_PHY1_OFFSET			10
+#define MXC_CCM_CCGR4_USB_PHY2_OFFSET			12
+#endif
+#define MXC_CCM_CCGR4_SAHARA_OFFSET			14
+#define MXC_CCM_CCGR4_RTIC_OFFSET			16
+#define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET			18
+#define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET			20
+#define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET			22
+#define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET			24
+#define MXC_CCM_CCGR4_CSPI_IPG_OFFSET			26
+#define MXC_CCM_CCGR4_SRTC_OFFSET			28
+#define MXC_CCM_CCGR4_SDMA_OFFSET			30
+
+#define MXC_CCM_CCGR5_SPBA_OFFSET			0
+#define MXC_CCM_CCGR5_GPU_OFFSET			2
+#define MXC_CCM_CCGR5_GARB_OFFSET			4
+#define MXC_CCM_CCGR5_VPU_OFFSET			6
+#define MXC_CCM_CCGR5_VPU_REF_OFFSET			8
+#define MXC_CCM_CCGR5_IPU_OFFSET			10
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_IPUMUX12_OFFSET			12
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR5_IPUMUX1_OFFSET			12
+#endif
+#define MXC_CCM_CCGR5_EMI_FAST_OFFSET			14
+#define MXC_CCM_CCGR5_EMI_SLOW_OFFSET			16
+#define MXC_CCM_CCGR5_EMI_INT1_OFFSET			18
+#define MXC_CCM_CCGR5_EMI_ENFC_OFFSET			20
+#define MXC_CCM_CCGR5_EMI_WRCK_OFFSET			22
+#define MXC_CCM_CCGR5_GPC_IPG_OFFSET			24
+#define MXC_CCM_CCGR5_SPDIF0_OFFSET			26
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_SPDIF1_OFFSET			28
+#endif
+#define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET			30
+
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_IPUMUX2_OFFSET			0
+#define MXC_CCM_CCGR6_OCRAM_OFFSET			2
+#endif
+#define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET			4
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET			6
+#define MXC_CCM_CCGR6_EMI_GARB_OFFSET			8
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_EMI_INT2_OFFSET			8
+#endif
+#define MXC_CCM_CCGR6_IPU_DI0_OFFSET			10
+#define MXC_CCM_CCGR6_IPU_DI1_OFFSET			12
+#define MXC_CCM_CCGR6_GPU2D_OFFSET			14
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_ESAI_IPG_OFFSET			16
+#define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET			18
+#define MXC_CCM_CCGR6_CAN1_IPG_OFFSET			20
+#define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET		22
+#define MXC_CCM_CCGR6_PL301_4X1_OFFSET			24
+#define MXC_CCM_CCGR6_PL301_2X2_OFFSET			26
+#define MXC_CCM_CCGR6_LDB_DI0_OFFSET			28
+#define MXC_CCM_CCGR6_LDB_DI1_OFFSET			30
+
+#define MXC_CCM_CCGR7_ASRC_IPG_OFFSET			0
+#define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET			2
+#define MXC_CCM_CCGR7_MLB_OFFSET			4
+#define MXC_CCM_CCGR7_IEEE1588_OFFSET			6
+#define MXC_CCM_CCGR7_UART4_IPG_OFFSET			8
+#define MXC_CCM_CCGR7_UART4_PER_OFFSET			10
+#define MXC_CCM_CCGR7_UART5_IPG_OFFSET			12
+#define MXC_CCM_CCGR7_UART5_PER_OFFSET			14
+#endif
 
 /* Define the bits in register CLPCR */
 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                 (0x1 << 18)
diff --git u-boot-4d3c95f.orig/drivers/usb/host/ehci-mx5.c u-boot-4d3c95f/drivers/usb/host/ehci-mx5.c
index 58cdcbe..079c567 100644
--- u-boot-4d3c95f.orig/drivers/usb/host/ehci-mx5.c
+++ u-boot-4d3c95f/drivers/usb/host/ehci-mx5.c
@@ -221,8 +221,13 @@ int ehci_hcd_init(void)
 
 	set_usboh3_clk();
 	enable_usboh3_clk(1);
+#if defined(CONFIG_MX51) && CONFIG_MXC_USB_PORT == 0
+	set_usb_phy_clk();
+	enable_usb_phy_clk(1);
+#elif defined(CONFIG_MX53)
 	set_usb_phy2_clk();
 	enable_usb_phy2_clk(1);
+#endif
 	mdelay(1);
 
 	/* Do board specific initialization */
diff --git u-boot-4d3c95f.orig/drivers/video/ipu_common.c u-boot-4d3c95f/drivers/video/ipu_common.c
index 2020da9..7869d65 100644
--- u-boot-4d3c95f.orig/drivers/video/ipu_common.c
+++ u-boot-4d3c95f/drivers/video/ipu_common.c
@@ -213,7 +213,7 @@ static struct clk ipu_clk = {
 	.rate = CONFIG_IPUV3_CLK,
 	.enable_reg = (u32 *)(CCM_BASE_ADDR +
 		offsetof(struct mxc_ccm_reg, CCGR5)),
-	.enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
+	.enable_shift = MXC_CCM_CCGR5_IPU_OFFSET,
 	.enable = clk_ipu_enable,
 	.disable = clk_ipu_disable,
 	.usecount = 0,
