| Message ID | 20241006222148.16456-1-andre.przywara@arm.com |
|---|---|
| State | Accepted |
| Delegated to: | Andre Przywara |
| Headers | show |
| Series | clk: sunxi: a80: Fix reset description | expand |
On Mon, Oct 7, 2024 at 6:22 AM Andre Przywara <andre.przywara@arm.com> wrote: > > Clock gates and reset lines share a common structure in the sunxi clock > driver descriptions, but use different flags to tell them apart. > > The description of the Allwinner A80 MMC clock reset lines was > erroneously using the "GATE" macro, which made the reset driver ignore > that entry, complaining with: > sunxi_set_reset: (RST-reset:#0) unhandled > > Change that to the correct "RESET" macro, to make the reset driver > happy. > > Fixes e0c7ce7e52b7 ("sunxi: clk: A80: add MMC clock support") > Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> > --- > drivers/clk/sunxi/clk_a80.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c > index e26d42a5e71..4e37fa39986 100644 > --- a/drivers/clk/sunxi/clk_a80.c > +++ b/drivers/clk/sunxi/clk_a80.c > @@ -77,10 +77,10 @@ static const struct ccu_clk_gate a80_mmc_gates[] = { > }; > > static const struct ccu_reset a80_mmc_resets[] = { > - [0] = GATE(0x0, BIT(18)), > - [1] = GATE(0x4, BIT(18)), > - [2] = GATE(0x8, BIT(18)), > - [3] = GATE(0xc, BIT(18)), > + [0] = RESET(0x0, BIT(18)), > + [1] = RESET(0x4, BIT(18)), > + [2] = RESET(0x8, BIT(18)), > + [3] = RESET(0xc, BIT(18)), > }; > > static const struct ccu_clk_gate a80_usb_gates[] = { > -- > 2.46.2 >
diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index e26d42a5e71..4e37fa39986 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -77,10 +77,10 @@ static const struct ccu_clk_gate a80_mmc_gates[] = { }; static const struct ccu_reset a80_mmc_resets[] = { - [0] = GATE(0x0, BIT(18)), - [1] = GATE(0x4, BIT(18)), - [2] = GATE(0x8, BIT(18)), - [3] = GATE(0xc, BIT(18)), + [0] = RESET(0x0, BIT(18)), + [1] = RESET(0x4, BIT(18)), + [2] = RESET(0x8, BIT(18)), + [3] = RESET(0xc, BIT(18)), }; static const struct ccu_clk_gate a80_usb_gates[] = {
Clock gates and reset lines share a common structure in the sunxi clock driver descriptions, but use different flags to tell them apart. The description of the Allwinner A80 MMC clock reset lines was erroneously using the "GATE" macro, which made the reset driver ignore that entry, complaining with: sunxi_set_reset: (RST-reset:#0) unhandled Change that to the correct "RESET" macro, to make the reset driver happy. Fixes e0c7ce7e52b7 ("sunxi: clk: A80: add MMC clock support") Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- drivers/clk/sunxi/clk_a80.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)