[v1,18/20] configs: socfpga: soc64: agilex5: Enable XGMAC

Message ID	20240920070242.20884-19-tien.fong.chee@intel.com
State	New
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut <marex@denx.de>, Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>, Meng Tingting <tingting.meng@intel.com>, Yuslaimi Alif Zakuan <alif.zakuan.yuslaimi@intel.com>, Hea Kok Kiang <kok.kiang.hea@intel.com>, Tien Fong Chee <tien.fong.chee@intel.com> Subject: [PATCH v1 18/20] configs: socfpga: soc64: agilex5: Enable XGMAC Date: Fri, 20 Sep 2024 15:02:40 +0800 Message-Id: <20240920070242.20884-19-tien.fong.chee@intel.com> In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com> References: <20240920070242.20884-1-tien.fong.chee@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	SoCFPGA: Add Boot Support for Agilex 5 in U-Boot \| expand [v1,00/20] SoCFPGA: Add Boot Support for Agilex 5 in U-Boot [v1,01/20] arm: socfpga: agilex5: Add new system manager base addresses [v1,02/20] arm: socfpga: Add support for agilex5 clock manager [v1,03/20] linker: Add SPL linker script for SoC64 devices [v1,04/20] arm: socfpga: agilex5: Add low level initialization [v1,05/20] arm: socfpga: Add handoff data support for SoCFPGA Agilex5 device [v1,06/20] arm: dts: agilex5: Add HPS cache coherency unit configuration settings [v1,07/20] arm: dts: agilex5: Add firewall configure settings [v1,08/20] arm: dts: agilex5: Enable XGMAC [v1,09/20] sysreset: Add reset support to SoCFPGA Agilex5 device [v1,10/20] arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU [v1,11/20] arm: socfpga: agilex5: Add SMMU initialization [v1,12/20] arm: socfpga: agilex5: Update CPU info [v1,13/20] arm: socfpga: Export board ID as U-Boot environment variable [v1,14/20] configs: agilex5: Add configuration for malloc pool [v1,15/20] arm: socfpga: smc: Add memory coherency support to mailbox command [v1,16/20] ddr: altera: Add DDR driver for Agilex5 series [v1,17/20] arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGA [v1,18/20] configs: socfpga: soc64: agilex5: Enable XGMAC [v1,19/20] arm: socfpga: soc64: Add support for board_boot_order() [v1,20/20] configs: socfpga: soc64: agilex5: Enable QSPI boot with UBI / UBIFS

Message ID

20240920070242.20884-19-tien.fong.chee@intel.com

State

New

Headers

From: tien.fong.chee@intel.com
To: u-boot@lists.denx.de
Cc: Marek Vasut <marex@denx.de>,
 Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
 Meng Tingting <tingting.meng@intel.com>,
 Yuslaimi Alif Zakuan <alif.zakuan.yuslaimi@intel.com>,
 Hea Kok Kiang <kok.kiang.hea@intel.com>,
 Tien Fong Chee <tien.fong.chee@intel.com>
Subject: [PATCH v1 18/20] configs: socfpga: soc64: agilex5: Enable XGMAC
Date: Fri, 20 Sep 2024 15:02:40 +0800
Message-Id: <20240920070242.20884-19-tien.fong.chee@intel.com>
In-Reply-To: <20240920070242.20884-1-tien.fong.chee@intel.com>
References: <20240920070242.20884-1-tien.fong.chee@intel.com>
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Series

SoCFPGA: Add Boot Support for Agilex 5 in U-Boot | expand

Commit Message

Chee, Tien Fong Sept. 20, 2024, 7:02 a.m. UTC

From: Tien Fong Chee <tien.fong.chee@intel.com>

Enable XGMAC for SoCFPGA Agilex5 devkit.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 configs/socfpga_agilex5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig
index 81bbe967dcf..a4a5064d9c2 100644
--- a/configs/socfpga_agilex5_defconfig
+++ b/configs/socfpga_agilex5_defconfig
@@ -92,3 +92,4 @@  CONFIG_WDT=y
 CONFIG_PANIC_HANG=y
 CONFIG_SPL_CRC32=y
 # CONFIG_EFI_LOADER is not set
+CONFIG_DWC_ETH_XGMAC=y

[v1,18/20] configs: socfpga: soc64: agilex5: Enable XGMAC

Commit Message

Patch