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Fri, 20 Sep 2024 01:00:41 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-378e7800313sm17059497f8f.88.2024.09.20.01.00.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Sep 2024 01:00:41 -0700 (PDT) From: neil.armstrong@linaro.org Date: Fri, 20 Sep 2024 10:00:31 +0200 Subject: [PATCH v2 10/13] ufs: Add missing memory barriers MIME-Version: 1.0 Message-Id: <20240920-topic-ufs-enhancements-v2-10-65ae61e73eaa@linaro.org> References: <20240920-topic-ufs-enhancements-v2-0-65ae61e73eaa@linaro.org> In-Reply-To: <20240920-topic-ufs-enhancements-v2-0-65ae61e73eaa@linaro.org> To: Tom Rini , Bhupesh Sharma , Neha Malcom Francis Cc: Michal Simek , Marek Vasut , bmeng.cn@gmail.com, u-boot@lists.denx.de, u-boot-qcom@groups.io, Neil Armstrong , Venkatesh Yadav Abbarapu , Bhupesh Sharma X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1907; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=VH31kyx3vGlBvfPTBzFzjs7QQX5ry7nhhEz711qZ8eg=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBm7SudITlYBYW4VtV7kARszN9PbbU14MjvwAqJZpG/ LqnwuD+JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZu0rnQAKCRB33NvayMhJ0cpnEA DMvYZ5wVaJKtU/g7M06PPcGlnYFR2e9m1DBtTHWgeK7hTQuf1C+cTF/30LmCmFDK+tnbviwwtwv2wK 0S7JcQHX+a5gAW9/Njv820rd/6V0eDY6X8nMmkrbVQ7qYNPPcOK7Tx6J1opM4NICHJxZ3EYAzgIUlt 3/CW3mHrhoH+g7nWl0DSqfAxLrcxuSoy62CD/EN+AXQYVwcRPRpimPVNuh5i/fM62TMetwO9ec8JFy Kz8htx/X5yxuDh+fYbzzOD6EDg+OYAfZZ2/+/u8o7RzGYxfR2wrqx07XljpsRwICOUJDusmUiTRFO+ Qj9d0YxRDL8jk2fNS9x6xCzpAw8ViId57W6YUOREeSoX/SGGb0bzKDkJJrvpQU689D8zjDfp8Y6Xpu rMMarj7LMH41DPLF1cPVU3uU7huqrw3sGD8O2uWdxw6n/09TlSDKrz+KKfdyWzzfykjVRP9doKvxvj Gyw1OZqLl+gPU75b3bmnMCc3h357GOXD6js0B8bXjqfiP7pEJ6h8Z3LbuurpuBNjphkN68auSMZSD7 DWzEG/SmbAQtjMsi0Rqd603R1nCoBMfZ3j4OIXoqC2IcvWX8ewoCoeMlit6dJ4Px+/fEdfrEGrk6Fm ikRt6Xw9aPTvpZsnEyk/3HmxQgt9EmKmiflpelt27ZaZFhJf9eu2OMgk8m7w== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Bhupesh Sharma Add missing wmb() and mb() barriers in the u-boot UFS core framework driver to allow registers updates to happen before follow-up read operations. This makes the barrier placement similar to the Linux UFS driver, synced from the Linux v6.9 release. Starting from the v6.10 release, the barriers were replaced with a register read-back in [1], this will ported to u-boot in a second time. [1] https://lore.kernel.org/all/20240329-ufs-reset-ensure-effect-before-delay-v5-0-181252004586@redhat.com/ Signed-off-by: Bhupesh Sharma Tested-by: Venkatesh Yadav Abbarapu --- drivers/ufs/ufs.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c index 565a6af1404..5d4e5424358 100644 --- a/drivers/ufs/ufs.c +++ b/drivers/ufs/ufs.c @@ -432,6 +432,12 @@ static int ufshcd_make_hba_operational(struct ufs_hba *hba) ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl), REG_UTP_TASK_REQ_LIST_BASE_H); + /* + * Make sure base address and interrupt setup are updated before + * enabling the run/stop registers below. + */ + wmb(); + /* * UCRDY, UTMRLDY and UTRLRDY bits must be 1 */ @@ -861,6 +867,9 @@ static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag) ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL); + /* Make sure doorbell reg is updated before reading interrupt status */ + wmb(); + start = get_timer(0); do { intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); @@ -1994,6 +2003,8 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops) REG_INTERRUPT_STATUS); ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); + mb(); + err = ufshcd_hba_enable(hba); if (err) { dev_err(hba->dev, "Host controller enable failed\n");