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d="scan'208";a="43178045" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2024 20:56:17 -0700 X-CSE-ConnectionGUID: d1xRwenvSkWiDVDVBPq8+Q== X-CSE-MsgGUID: e80tmM20TES2bjsuZ6gfTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,240,1719903600"; d="scan'208";a="70253802" Received: from pglc00481.png.intel.com ([10.221.239.164]) by orviesa007.jf.intel.com with ESMTP; 18 Sep 2024 20:56:12 -0700 From: dinesh.maniyam@intel.com To: u-boot@lists.denx.de Cc: Marek , Simon , Tom Rini , Dario Binacchi , Michael Trimarchi , Johan Jonker , Michal Simek , Arseniy Krasnov , Alexander Dahl , William Zhang , Igor Prusov , Tien Fong , Kok Kiang , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Tingting Meng , Jit Loon Lim , Sieu Mun Tang Subject: [PATCH 10/19] drivers: mtd: nand: cadence: Flush dma descriptor Date: Thu, 19 Sep 2024 11:55:03 +0800 Message-Id: <20240919035512.13854-11-dinesh.maniyam@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20240919035512.13854-1-dinesh.maniyam@intel.com> References: <20240919035512.13854-1-dinesh.maniyam@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Dinesh Maniyam The patch is to ensure ddr memory is updated with the data from dcache, This would help to ensure cdma always reading the latest dma descriptor in ddr memory. Signed-off-by: Dinesh Maniyam --- drivers/mtd/nand/raw/cadence_nand.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/nand/raw/cadence_nand.c b/drivers/mtd/nand/raw/cadence_nand.c index 108e1fa965..429a5e8017 100644 --- a/drivers/mtd/nand/raw/cadence_nand.c +++ b/drivers/mtd/nand/raw/cadence_nand.c @@ -429,6 +429,10 @@ cadence_nand_cdma_desc_prepare(struct cadence_nand_info *cadence, cdma_desc->command_type = ctype; cdma_desc->ctrl_data_ptr = ctrl_data_ptr; + + flush_cache((dma_addr_t)cadence->cdma_desc, + ROUND(sizeof(struct cadence_nand_cdma_desc), + ARCH_DMA_MINALIGN)); } static u8 cadence_nand_check_desc_error(struct cadence_nand_info *cadence,