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Tue, 10 Sep 2024 02:20:29 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42cb099acf6sm101256245e9.9.2024.09.10.02.20.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Sep 2024 02:20:29 -0700 (PDT) From: Neil Armstrong Date: Tue, 10 Sep 2024 11:20:19 +0200 Subject: [PATCH 02/13] ufs: fix dcache flush and invalidate range calculation MIME-Version: 1.0 Message-Id: <20240910-topic-ufs-enhancements-v1-2-3ee0bffacc64@linaro.org> References: <20240910-topic-ufs-enhancements-v1-0-3ee0bffacc64@linaro.org> In-Reply-To: <20240910-topic-ufs-enhancements-v1-0-3ee0bffacc64@linaro.org> To: Tom Rini , Bhupesh Sharma , Neha Malcom Francis Cc: u-boot@lists.denx.de, u-boot-qcom@groups.io, Neil Armstrong X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1874; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=oVsz8gmXWVEZJZf1Mg+oM6GpP73pR3b7jLP7OPiK+Sw=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBm4A9WNWc17o2C698+AIILxdeWPed6pOpY1TgDkvuA gHbQilKJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZuAPVgAKCRB33NvayMhJ0WieEA CHNb2WSHPIYL9cqYeBBoFm+aJSg/lqQVjg+g/b6gO+yWVC6h76+N4DjGB2TbyYgfzwA7fXzQfGTA6/ 4BACxlFu2yPWh5gOU6htvsABQE39OioBIlM7vnNLFLvprBCPfOzb2SAMQ5a5sHY4xhOuQUqZjw+AJE dDxJ2BfL1iHWpwriLA1UTqWcGahY43dUTfuY5uzC7zGl9LppqpOjxohqWwHkmfa2ZpnrwC4pNIcBVT ptrBk/yoHm9krleb814GOmzDxp4JRRfdQzxAa2tnXI7kAGSem8JuVVTy+EzCkl7iOkYJonNaMZUR2p /+ebnr3Iw4rEs0qcYEC+L+oqUSGX66oYZJnfbEU8TgxbGsj0YFFK9XRaNBpZzIaXxwyM5x5a4fiKpx b4yh/8GizQaLfoWVYUppYrPyv0ktUE5C7hFBDGH8REOxiQR4h7ptpHhcPBIugDGpxybnVOrZgMmOE1 0CsLJeijS5/OyO7GkHORSqKhBU1ZV4DaTgn8rvuRHttm5rouNdto7gWuJkwxlQWlUQVGs9X7B8jZWx tes3L7BHyJ3DhUhCKLBl+D2FhMChCiSzaCXu+ttP85PnAkClMSwZ02Iqo4NF8gwl4D2VKhiE4wLmzP 1rgCfvzyJOz/vzIhSrzIKPPtOpqfwoI4Xb0UwNxHAJ0legM3LB2Zt1NG/4SQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The current calculation will omit doing a flush/invalidate on the last cacheline if the base address is not aligned with DMA_MINALIGN. This causes commands failures and write corruptions on Qualcomm platforms. Signed-off-by: Neil Armstrong Reviewed-by: Neha Malcom Francis --- drivers/ufs/ufs.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c index e005cc90608..3d9a7d7ee12 100644 --- a/drivers/ufs/ufs.c +++ b/drivers/ufs/ufs.c @@ -703,11 +703,11 @@ static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) */ static void ufshcd_cache_flush_and_invalidate(void *addr, unsigned long size) { - uintptr_t aaddr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); - unsigned long asize = ALIGN(size, ARCH_DMA_MINALIGN); + uintptr_t start_addr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); + uintptr_t end_addr = ALIGN((uintptr_t)addr + size, ARCH_DMA_MINALIGN); - flush_dcache_range(aaddr, aaddr + asize); - invalidate_dcache_range(aaddr, aaddr + asize); + flush_dcache_range(start_addr, end_addr); + invalidate_dcache_range(start_addr, end_addr); } /** @@ -1466,13 +1466,13 @@ static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb) } if (pccb->dma_dir == DMA_TO_DEVICE) { /* Write to device */ - flush_dcache_range(aaddr, aaddr + - ALIGN(datalen, ARCH_DMA_MINALIGN)); + flush_dcache_range(aaddr, + ALIGN((uintptr_t)pccb->pdata + datalen, ARCH_DMA_MINALIGN)); } /* In any case, invalidate cache to avoid stale data in it. */ - invalidate_dcache_range(aaddr, aaddr + - ALIGN(datalen, ARCH_DMA_MINALIGN)); + invalidate_dcache_range(aaddr, + ALIGN((uintptr_t)pccb->pdata + datalen, ARCH_DMA_MINALIGN)); table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY); buf = pccb->pdata;