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Tue, 20 Aug 2024 02:38:41 -0700 (PDT) Received: from localhost.localdomain ([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id 5614622812f47-3dd33d3fe91sm2795674b6e.9.2024.08.20.02.38.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 02:38:41 -0700 (PDT) From: Mayuresh Chitale To: u-boot@lists.denx.de Cc: Mayuresh Chitale , Bin Meng , Tom Rini , =?utf-8?q?=C5=81ukasz_Stelmach?= , Leo Yu-Chi Liang Subject: [PATCH v1 3/3] board: qemu-riscv: Override enable_caches Date: Tue, 20 Aug 2024 09:37:52 +0000 Message-Id: <20240820093800.5436-4-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240820093800.5436-1-mchitale@ventanamicro.com> References: <20240820093800.5436-1-mchitale@ventanamicro.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Define enable_caches function for the qemu-riscv board which probes for the cbom-block-size dt property when RISCV_ISA_ZICBOM is enabled. Also add flush_dcache_range and invalidate_dcache_range functions which use the corresponding CBO ops. Signed-off-by: Mayuresh Chitale --- board/emulation/qemu-riscv/qemu-riscv.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index e5193e31e3..1795d2f831 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -14,6 +14,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -70,3 +71,18 @@ void *board_fdt_blob_setup(int *err) /* Stored the DTB address there during our init */ return (void *)(ulong)gd->arch.firmware_fdt_addr; } + +void enable_caches(void) +{ + riscv_zicbom_init(); +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + cbo_flush(start, end); +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + cbo_inval(start, end); +}