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Mon, 5 Aug 2024 09:30:15 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 5 Aug 2024 09:30:15 -0500 Received: from lcpd911.dhcp.ti.com (lcpd911.dhcp.ti.com [172.24.227.68]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 475ETihr084343; Mon, 5 Aug 2024 09:30:10 -0500 From: Dhruva Gole To: Tom Rini , Nishant Menon CC: , Neha Malcom Francis , , , , Robert Nelson , Vibhore Vardhan , Vishal Mahaveer , Sebin Francis , Wadim Egorov , , , Daniel Schultz , Dhruva Gole Subject: [PATCH V8 4/7] doc: ti: am62*: Mention TIFS Stub in img fmts and boot flow Date: Mon, 5 Aug 2024 19:59:34 +0530 Message-ID: <20240805142937.443737-5-d-gole@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240805142937.443737-1-d-gole@ti.com> References: <20240805142937.443737-1-d-gole@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Since AM62x, AM62P and AM62A all use similar boot flows and their low power mode s/w ARCH is also similar in the way that they make use of the TIFS Stub, update their documentation to show where TIFS Stub is. Reviewed-by: Nishanth Menon Signed-off-by: Dhruva Gole --- doc/board/ti/am62ax_sk.rst | 4 +- doc/board/ti/am62px_sk.rst | 4 +- doc/board/ti/am62x_sk.rst | 4 +- doc/board/ti/img/boot_diagram_am62.svg | 1983 ++++++++++++++++++++ doc/board/ti/img/tifsstub_dm_tispl.bin.svg | 353 ++++ 5 files changed, 2342 insertions(+), 6 deletions(-) create mode 100644 doc/board/ti/img/boot_diagram_am62.svg create mode 100644 doc/board/ti/img/tifsstub_dm_tispl.bin.svg diff --git a/doc/board/ti/am62ax_sk.rst b/doc/board/ti/am62ax_sk.rst index 72fa5a8d8cdd..262340ef59a3 100644 --- a/doc/board/ti/am62ax_sk.rst +++ b/doc/board/ti/am62ax_sk.rst @@ -47,7 +47,7 @@ Boot Flow: ---------- Below is the pictorial representation of boot flow: -.. image:: img/boot_diagram_k3_current.svg +.. image:: img/boot_diagram_am62.svg :alt: Boot flow diagram - Here TIFS acts as master and provides all the critical services. R5/A53 @@ -148,7 +148,7 @@ Image formats: - tispl.bin -.. image:: img/dm_tispl.bin.svg +.. image:: img/tifsstub_dm_tispl.bin.svg :alt: tispl.bin image format Switch Setting for Boot Mode diff --git a/doc/board/ti/am62px_sk.rst b/doc/board/ti/am62px_sk.rst index bcef6653cb92..99bdc0348692 100644 --- a/doc/board/ti/am62px_sk.rst +++ b/doc/board/ti/am62px_sk.rst @@ -55,7 +55,7 @@ Boot Flow: The bootflow is exactly the same as all SoCs in the am62xxx extended SoC family. Below is the pictorial representation: -.. image:: img/boot_diagram_k3_current.svg +.. image:: img/boot_diagram_am62.svg :alt: Boot flow diagram - Here TIFS acts as master and provides all the critical services. R5/A53 @@ -157,7 +157,7 @@ Image formats: - tispl.bin -.. image:: img/dm_tispl.bin.svg +.. image:: img/tifsstub_dm_tispl.bin.svg :alt: tispl.bin image format OSPI: diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst index e2a848d159ff..b9d35244d446 100644 --- a/doc/board/ti/am62x_sk.rst +++ b/doc/board/ti/am62x_sk.rst @@ -46,7 +46,7 @@ Boot Flow: ---------- Below is the pictorial representation of boot flow: -.. image:: img/boot_diagram_k3_current.svg +.. image:: img/boot_diagram_am62.svg :alt: Boot flow diagram - Here TIFS acts as master and provides all the critical services. R5/A53 @@ -165,7 +165,7 @@ Image formats: - tispl.bin -.. image:: img/dm_tispl.bin.svg +.. image:: img/tifsstub_dm_tispl.bin.svg :alt: tispl.bin image format OSPI: diff --git a/doc/board/ti/img/boot_diagram_am62.svg b/doc/board/ti/img/boot_diagram_am62.svg new file mode 100644 index 000000000000..44c54dbd2c1e --- /dev/null +++ b/doc/board/ti/img/boot_diagram_am62.svg @@ -0,0 +1,1983 @@ + + + + + + + + + + + + + + + + + + Cortex-R + + + + Cortex-R + + + + + + + + + + ROM + + + + ROM + + + + + + + + + + Cortex-R SPL + + + + Cortex-R SPL + + + + + + + + + Load and auth tiboot3.bin + + + + Load and auth t... + + + + + + + + + Load system +config data + + + + Load system... + + + + + + + + + DDR Config + + + + DDR Config + + + + + + + + + Load tispl.bin + + + + Load tispl.bin + + + + + + + + + Start Cortex-A + + + + Start Cortex-A + + + + + + + + + Start DM + + + + Start DM + + + + + + + + + + + + Device Mgr + + + + Device Mgr + + + + + + + + + + Start Cortex-A + + + + Start Cort... + + + + + + + + + + + + + + + + + + + + + Load TIFS Stub in TCM + + + + Load TIFS St... + + + + + + + + + + + + Cortex-A + + + + Cortex-A + + + + + + + + + + + + + + OP-TEE + + + + OP-TEE + + + + + + + + + + Cortex-R/M +C6x/C7x + + + + Cortex-R/M... + + + + + + + + + + Aux f/w + + + + Aux f/w + + + + + + + + + + TIFS/DMSC + + + + TIFS/DMSC + + + + + + + + + + ROM + + + + ROM + + + + + + + + + + + Start TIFS + + + + Start TIFS + + + + + + + + + TIFS + + + + TIFS + + + + + + + + + + Security Enclave Boot Processor + + + + Security Enclave Boot... + + + + + + + + + + Boot Loader +Processor + + + + Boot Loader... + + + + + + + + + + Main CPU + + + + Main CPU + + + + + + + + + + Auxiliary +Processor + + + + Auxiliary... + + + + + + + + + + H/w Seq: Reset rls + + + + H/w Seq: Reset rls + + + + + + + + + + Auth tiboot3.bin + + + + Auth tiboo... + + + + + + + + + + Release Reset + + + + Release Re... + + + + + + + + + + Load system config data + + + + Load syste... + + + + + + + + + Start TIFS + + + + Start TIFS + + + + + + + + + Load DM f/w + + + + Load DM f/w + + + + + + + + + + branch + + + + branch + + + + + + + + + + Release Reset + + + + Release Re... + + + + + + + + + TF-A  + + + + TF-A  + + + + + + + + + + Cortex-A SPL + + + + Cortex-A SPL + + + + + + + + + + U-Boot + + + + U-Boot + + + + + + + + + Load u-boot.img + + + + Load u-boot.img + + + + + + + + + Load Aux core f/w +(optional) + + + + Load Aux core f/w... + + + + + + + + + Start Aux core +(optional) + + + + Start Aux core... + + + + + + + + + + Release Reset + + + + Release Re... + + + + + + + Text is not SVG - cannot display + + + diff --git a/doc/board/ti/img/tifsstub_dm_tispl.bin.svg b/doc/board/ti/img/tifsstub_dm_tispl.bin.svg new file mode 100644 index 000000000000..5d56d81f6674 --- /dev/null +++ b/doc/board/ti/img/tifsstub_dm_tispl.bin.svg @@ -0,0 +1,353 @@ + + + + + + + + + + + + + + + + + FIT Header + + + + FIT Header + + + + + + + + + TIFS Stub +(GP, HS-FS, HS-SE) + + + + TIFS Stub... + + + + + + + + + TF-A + + + + TF-A + + + + + + + + + OP-TEE + + + + OP-TEE + + + + + + + + + R5 DM FW + + + + R5 DM FW + + + + + + + + + Cortex-A SPL + + + + Cortex-A SPL + + + + + + + + + SPL DTB 1..N + + + + SPL DTB 1..N + + + + + + + Text is not SVG - cannot display + + +