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[87.6.196.30]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-428e6d648a0sm63835655e9.10.2024.08.03.04.13.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 03 Aug 2024 04:13:08 -0700 (PDT) From: Christian Marangi To: Lukasz Majewski , Sean Anderson , Ryder Lee , Weijie Gao , Chunfeng Yun , GSS_MTK_Uboot_upstream , Tom Rini , Christian Marangi , u-boot@lists.denx.de Subject: [PATCH v2 6/8] clk: mediatek: mt7622: add missing clock PERI_UART4_PD Date: Sat, 3 Aug 2024 10:43:24 +0200 Message-ID: <20240803084329.1688-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240803084329.1688-1-ansuelsmth@gmail.com> References: <20240803084329.1688-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add missing clock PERI_UART4_PD for peri clock gates. This is needed to match upstream linux clk ID in preparation for OF_UPSTREAM. Also convert infracfg to mux + gate implementation as now we have mux on top of gates. Signed-off-by: Christian Marangi --- drivers/clk/mediatek/clk-mt7622.c | 1 + include/dt-bindings/clock/mt7622-clk.h | 25 +++++++++++++------------ 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 0da7a848163..5df62e64c9a 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -472,6 +472,7 @@ static const struct mtk_gate peri_cgs[] = { GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18), GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19), GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20), + GATE_PERI0(CLK_PERI_UART4_PD, CLK_TOP_AXI_SEL, 21), GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22), GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23), GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24), diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index 0820fab0a22..4b6501c1020 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -146,18 +146,19 @@ #define CLK_PERI_UART1_PD 13 #define CLK_PERI_UART2_PD 14 #define CLK_PERI_UART3_PD 15 -#define CLK_PERI_BTIF_PD 16 -#define CLK_PERI_I2C0_PD 17 -#define CLK_PERI_I2C1_PD 18 -#define CLK_PERI_I2C2_PD 19 -#define CLK_PERI_SPI1_PD 20 -#define CLK_PERI_AUXADC_PD 21 -#define CLK_PERI_SPI0_PD 22 -#define CLK_PERI_SNFI_PD 23 -#define CLK_PERI_NFI_PD 24 -#define CLK_PERI_NFIECC_PD 25 -#define CLK_PERI_FLASH_PD 26 -#define CLK_PERI_IRTX_PD 27 +#define CLK_PERI_UART4_PD 16 +#define CLK_PERI_BTIF_PD 17 +#define CLK_PERI_I2C0_PD 18 +#define CLK_PERI_I2C1_PD 19 +#define CLK_PERI_I2C2_PD 20 +#define CLK_PERI_SPI1_PD 21 +#define CLK_PERI_AUXADC_PD 22 +#define CLK_PERI_SPI0_PD 23 +#define CLK_PERI_SNFI_PD 24 +#define CLK_PERI_NFI_PD 25 +#define CLK_PERI_NFIECC_PD 26 +#define CLK_PERI_FLASH_PD 27 +#define CLK_PERI_IRTX_PD 28 /* APMIXEDSYS */