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[87.6.196.30]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-36bbcf0dc9asm4085699f8f.15.2024.08.03.04.10.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 03 Aug 2024 04:10:42 -0700 (PDT) From: Christian Marangi To: Tom Rini , Lukasz Majewski , Sean Anderson , Ryder Lee , Weijie Gao , Chunfeng Yun , GSS_MTK_Uboot_upstream , Christian Marangi , u-boot@lists.denx.de Subject: [PATCH 06/15] clk: mediatek: mt7986: add missing entry for IPCIE_PIPE_CK infra gate Date: Sat, 3 Aug 2024 10:40:39 +0200 Message-ID: <20240803084050.449-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240803084050.449-1-ansuelsmth@gmail.com> References: <20240803084050.449-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add missing entry for IPCIE_PIPE_CK infra gate clock. Renumber the clock order to match the expected offset in the gate array. Signed-off-by: Christian Marangi --- drivers/clk/mediatek/clk-mt7986.c | 3 ++- include/dt-bindings/clock/mt7986-clk.h | 7 ++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c index f1870ce3d60..5f07de23756 100644 --- a/drivers/clk/mediatek/clk-mt7986.c +++ b/drivers/clk/mediatek/clk-mt7986.c @@ -336,7 +336,7 @@ static const struct mtk_parent infra_pwm_bsel_parents[] = { static const struct mtk_parent infra_pcie_parents[] = { TOP_PARENT(CK_TOP_CB_RTC_32P7K), TOP_PARENT(CK_TOP_F26M_SEL), - VOID_PARENT, + TOP_PARENT(CK_TOP_XTAL), TOP_PARENT(CK_TOP_PEXTP_TL_SEL) }; @@ -487,6 +487,7 @@ static const struct mtk_gate infracfg_ao_gates[] = { 2), GATE_INFRA2_TOP(CK_INFRA_IUSB_CK, "infra_iusb", CK_TOP_U2U3_SEL, 3), GATE_INFRA2_TOP(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_TOP_PEXTP_TL_SEL, 12), + GATE_INFRA2_TOP(CK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CK_TOP_XTAL, 13), GATE_INFRA2_TOP(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_TOP_F26M_SEL, 14), GATE_INFRA2_TOP(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_TOP_SYSAXI_SEL, 15), }; diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index dbae389858a..16faca5fef8 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -167,9 +167,10 @@ #define CK_INFRA_IUSB_SYS_CK 40 #define CK_INFRA_IUSB_CK 41 #define CK_INFRA_IPCIE_CK 42 -#define CK_INFRA_IPCIER_CK 43 -#define CK_INFRA_IPCIEB_CK 44 -#define CLK_INFRA_AO_NR_CLK 45 +#define CK_INFRA_IPCIE_PIPE_CK 43 +#define CK_INFRA_IPCIER_CK 44 +#define CK_INFRA_IPCIEB_CK 45 +#define CLK_INFRA_AO_NR_CLK 46 /* APMIXEDSYS */