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[87.6.196.30]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-36bbcf0dc9asm4085699f8f.15.2024.08.03.04.10.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 03 Aug 2024 04:10:35 -0700 (PDT) From: Christian Marangi To: Tom Rini , Lukasz Majewski , Sean Anderson , Ryder Lee , Weijie Gao , Chunfeng Yun , GSS_MTK_Uboot_upstream , Christian Marangi , u-boot@lists.denx.de Subject: [PATCH 01/15] clk: mediatek: mt7986: fix wrong shift for PCIe clocks Date: Sat, 3 Aug 2024 10:40:34 +0200 Message-ID: <20240803084050.449-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240803084050.449-1-ansuelsmth@gmail.com> References: <20240803084050.449-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Fix wrong shift for PCIe clocks. This cause the PCIe port to malfunction as the gate clocks weren't correctly enabled. Signed-off-by: Christian Marangi --- drivers/clk/mediatek/clk-mt7986.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c index efc3d4120b7..1e8c3278346 100644 --- a/drivers/clk/mediatek/clk-mt7986.c +++ b/drivers/clk/mediatek/clk-mt7986.c @@ -504,8 +504,8 @@ static const struct mtk_gate infracfg_ao_gates[] = { GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK, 2), GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3), - GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_INFRA_PCIE_CK, 13), - GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 15), + GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_INFRA_PCIE_CK, 12), + GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 14), GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15), };