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[87.6.196.30]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-36bbcf0dc9asm4085699f8f.15.2024.08.03.04.10.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 03 Aug 2024 04:10:49 -0700 (PDT) From: Christian Marangi To: Tom Rini , Lukasz Majewski , Sean Anderson , Ryder Lee , Weijie Gao , Chunfeng Yun , GSS_MTK_Uboot_upstream , Christian Marangi , u-boot@lists.denx.de Subject: [PATCH 12/15] clk: mediatek: mt7986: move INFRA_TRNG_CK to the bottom of the list Date: Sat, 3 Aug 2024 10:40:45 +0200 Message-ID: <20240803084050.449-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240803084050.449-1-ansuelsmth@gmail.com> References: <20240803084050.449-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Move INFRA_TRNG_CK to the bottom of the list to have a 1:1 match with upstream linux clock ID. Signed-off-by: Christian Marangi --- drivers/clk/mediatek/clk-mt7986.c | 3 +- include/dt-bindings/clock/mt7986-clk.h | 54 +++++++++++++------------- 2 files changed, 29 insertions(+), 28 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c index 08b7ab8a81e..7476024f584 100644 --- a/drivers/clk/mediatek/clk-mt7986.c +++ b/drivers/clk/mediatek/clk-mt7986.c @@ -470,7 +470,6 @@ static const struct mtk_gate infracfg_ao_gates[] = { GATE_INFRA0_INFRA(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_SYSAXI_D2, 16), GATE_INFRA0_INFRA(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_SYSAXI_D2, 24), GATE_INFRA0_TOP(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_TOP_F26M_SEL, 25), - GATE_INFRA0_TOP(CK_INFRA_TRNG_CK, "infra_trng", CK_TOP_SYSAXI_SEL, 26), /* INFRA1 */ GATE_INFRA1_TOP(CK_INFRA_THERM_CK, "infra_therm", CK_TOP_F26M_SEL, 0), GATE_INFRA1_TOP(CK_INFRA_I2C0_CK, "infra_i2co", CK_TOP_I2C_SEL, 1), @@ -511,6 +510,8 @@ static const struct mtk_gate infracfg_ao_gates[] = { GATE_INFRA2_TOP(CK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CK_TOP_XTAL, 13), GATE_INFRA2_TOP(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_TOP_F26M_SEL, 14), GATE_INFRA2_TOP(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_TOP_SYSAXI_SEL, 15), + /* upstream linux unordered */ + GATE_INFRA0_TOP(CK_INFRA_TRNG_CK, "infra_trng", CK_TOP_SYSAXI_SEL, 26), }; static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = { diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index 7df13665900..39939f8e028 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -115,33 +115,33 @@ #define CK_INFRA_SEJ_13M_CK 16 #define CK_INFRA_THERM_CK 17 #define CK_INFRA_I2C0_CK 18 -#define CK_INFRA_TRNG_CK 19 -#define CK_INFRA_UART0_CK 20 -#define CK_INFRA_UART1_CK 21 -#define CK_INFRA_UART2_CK 22 -#define CK_INFRA_NFI1_CK 23 -#define CK_INFRA_SPINFI1_CK 24 -#define CK_INFRA_NFI_HCK_CK 25 -#define CK_INFRA_SPI0_CK 26 -#define CK_INFRA_SPI1_CK 27 -#define CK_INFRA_SPI0_HCK_CK 28 -#define CK_INFRA_SPI1_HCK_CK 29 -#define CK_INFRA_FRTC_CK 30 -#define CK_INFRA_MSDC_CK 31 -#define CK_INFRA_MSDC_HCK_CK 32 -#define CK_INFRA_MSDC_133M_CK 33 -#define CK_INFRA_MSDC_66M_CK 34 -#define CK_INFRA_ADC_26M_CK 35 -#define CK_INFRA_ADC_FRC_CK 36 -#define CK_INFRA_FBIST2FPC_CK 37 -#define CK_INFRA_IUSB_133_CK 38 -#define CK_INFRA_IUSB_66M_CK 39 -#define CK_INFRA_IUSB_SYS_CK 40 -#define CK_INFRA_IUSB_CK 41 -#define CK_INFRA_IPCIE_CK 42 -#define CK_INFRA_IPCIE_PIPE_CK 43 -#define CK_INFRA_IPCIER_CK 44 -#define CK_INFRA_IPCIEB_CK 45 +#define CK_INFRA_UART0_CK 19 +#define CK_INFRA_UART1_CK 20 +#define CK_INFRA_UART2_CK 21 +#define CK_INFRA_NFI1_CK 22 +#define CK_INFRA_SPINFI1_CK 23 +#define CK_INFRA_NFI_HCK_CK 24 +#define CK_INFRA_SPI0_CK 25 +#define CK_INFRA_SPI1_CK 26 +#define CK_INFRA_SPI0_HCK_CK 27 +#define CK_INFRA_SPI1_HCK_CK 28 +#define CK_INFRA_FRTC_CK 29 +#define CK_INFRA_MSDC_CK 30 +#define CK_INFRA_MSDC_HCK_CK 31 +#define CK_INFRA_MSDC_133M_CK 32 +#define CK_INFRA_MSDC_66M_CK 33 +#define CK_INFRA_ADC_26M_CK 34 +#define CK_INFRA_ADC_FRC_CK 35 +#define CK_INFRA_FBIST2FPC_CK 36 +#define CK_INFRA_IUSB_133_CK 37 +#define CK_INFRA_IUSB_66M_CK 38 +#define CK_INFRA_IUSB_SYS_CK 39 +#define CK_INFRA_IUSB_CK 40 +#define CK_INFRA_IPCIE_CK 41 +#define CK_INFRA_IPCIE_PIPE_CK 42 +#define CK_INFRA_IPCIER_CK 43 +#define CK_INFRA_IPCIEB_CK 44 +#define CK_INFRA_TRNG_CK 45 #define CLK_INFRA_AO_NR_CLK 46 /* APMIXEDSYS */