| Message ID | 20240802135326.25303-4-ansuelsmth@gmail.com |
|---|---|
| State | Accepted |
| Delegated to: | Tom Rini |
| Headers | show
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[87.6.196.30]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-428e6e01d0asm43350485e9.16.2024.08.02.12.56.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Aug 2024 12:56:34 -0700 (PDT) From: Christian Marangi <ansuelsmth@gmail.com> To: Crispin John <john@phrozen.org>, Tom Rini <trini@konsulko.com>, Lukasz Majewski <lukma@denx.de>, Sean Anderson <seanga2@gmail.com>, Ryder Lee <ryder.lee@mediatek.com>, Weijie Gao <weijie.gao@mediatek.com>, Chunfeng Yun <chunfeng.yun@mediatek.com>, GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>, Christian Marangi <ansuelsmth@gmail.com>, Sam Shih <sam.shih@mediatek.com>, u-boot@lists.denx.de Subject: [PATCH 03/14] clk: mediatek: mt7981: fix wrong mux width for pwm2 and pwm1 clock Date: Fri, 2 Aug 2024 15:53:04 +0200 Message-ID: <20240802135326.25303-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240802135326.25303-1-ansuelsmth@gmail.com> References: <20240802135326.25303-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Unsubscribe: <https://lists.denx.de/options/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> List-Archive: <https://lists.denx.de/pipermail/u-boot/> List-Post: <mailto:u-boot@lists.denx.de> List-Help: <mailto:u-boot-request@lists.denx.de?subject=help> List-Subscribe: <https://lists.denx.de/listinfo/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=subscribe> Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de> X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean |
| Series |
clk: mediatek: mt7981: clk migration for OF_UPSTREAM
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diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 69d018b817a..6e770de99cf 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -404,9 +404,9 @@ static const struct mtk_composite infra_muxes[] = { INFRA_MUX(CK_INFRA_SPI2_SEL, "infra_spi2_sel", infra_spi0_parents, 0x10, 6, 1), INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm1_parents, 0x10, - 9, 2), + 9, 1), INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10, - 11, 2), + 11, 1), INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents, 0x10, 13, 2), INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
Fix wrong mux width for pwm2 and pwm1. Upstream have width 1 but U-Boot have width set to 2. Change the value to follow upstream implementation. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> --- drivers/clk/mediatek/clk-mt7981.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)