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[87.6.196.30]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-428e6e01d0asm43350485e9.16.2024.08.02.12.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Aug 2024 12:56:47 -0700 (PDT) From: Christian Marangi To: Crispin John , Tom Rini , Lukasz Majewski , Sean Anderson , Ryder Lee , Weijie Gao , Chunfeng Yun , GSS_MTK_Uboot_upstream , Christian Marangi , Sam Shih , u-boot@lists.denx.de Subject: [PATCH 12/14] clk: mediatek: mt7981: fix support for pwm3 clock Date: Fri, 2 Aug 2024 15:53:13 +0200 Message-ID: <20240802135326.25303-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240802135326.25303-1-ansuelsmth@gmail.com> References: <20240802135326.25303-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add and fix support for pwm3 clock. In the pwm DTSI node we were actually using PWM2 clock for PWM3. Now that we have correct ID also add the missing entry of gate and mux to support PWM3 clock. Signed-off-by: Christian Marangi --- arch/arm/dts/mt7981.dtsi | 3 +-- drivers/clk/mediatek/clk-mt7981.c | 3 +++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi index fc13b90caf6..b3f8a50cd10 100644 --- a/arch/arm/dts/mt7981.dtsi +++ b/arch/arm/dts/mt7981.dtsi @@ -144,8 +144,7 @@ <&infracfg_ao CK_INFRA_PWM_BSEL>, <&infracfg_ao CK_INFRA_PWM1_CK>, <&infracfg_ao CK_INFRA_PWM2_CK>, - /* FIXME */ - <&infracfg_ao CK_INFRA_PWM2_CK>; + <&infracfg_ao CK_INFRA_PWM3_CK>; assigned-clocks = <&topckgen CK_TOP_PWM_SEL>; assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>; clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 4435430dcde..7b692186dc1 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -381,6 +381,8 @@ static const struct mtk_composite infra_muxes[] = { 9, 1), INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10, 11, 1), + INFRA_MUX(CK_INFRA_PWM3_SEL, "infra_pwm3_sel", infra_pwm1_parents, 0x10, + 15, 1), INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents, 0x10, 13, 2), INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20, @@ -445,6 +447,7 @@ static const struct mtk_gate infracfg_ao_gates[] = { GATE_INFRA0_INFRA(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BSEL, 2), GATE_INFRA0_INFRA(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM1_SEL, 3), GATE_INFRA0_INFRA(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM2_SEL, 4), + GATE_INFRA0_INFRA(CK_INFRA_PWM3_CK, "infra_pwm3", CK_INFRA_PWM3_SEL, 27), GATE_INFRA0_TOP(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_TOP_SYSAXI, 6), GATE_INFRA0_TOP(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_TOP_SYSAXI, 8), GATE_INFRA0_TOP(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_TOP_F26M_SEL, 9),