| Message ID | 20240801083656.1936910-1-jonas@kwiboo.se |
|---|---|
| State | RFC |
| Delegated to: | Kever Yang |
| Headers | show |
| Series | [RFC] rockchip: rk3399: Migrate to use TPL on bob and kevin | expand |
Hi Jonas, On Thu, 1 Aug 2024 at 02:37, Jonas Karlman <jonas@kwiboo.se> wrote: > > All Rockchip aarch64 boards, beside bob and kevin, use TPL to initialize > DRAM and SPL to load FIT with U-Boot proper and TF-A. > > Bob and kevin currently does not use TPL and instead initialize DRAM > in SPL and directly after tries to load FIT with U-Boot proper and TF-A. > > This RFC try to migrate bob and kevin to also use TPL to uniform TPL/SPL > use for all Rockchip aarch64 boards. Thanks for doing this! > > Notes and questions: > - Is u-boot.rom even used for bob/kevin? It use u-boot-img, yet SPL > expect to load FIT and does not permit use of raw imgage. Yes it does use u-boot.rom > > Q: Can we remove what looks to be a faulty u-boot.rom definition and > just use u-boot-rockchip-spi.bin instead? Maybe, but we do need the image to be the correct size. > > - FIT location moved from 0x40000 to 0xE0000 in SPI flash to allow for a > larger SPL, up to 256 KiB, same as on other RK3399 boards. > > Q: Can we use this location?, or is there something external that > expects fit or u-boot-img at this location? It should be fine. > > Features that is now used: > - Use of Rockchip aarch64 common bss and stack addresses > - Checksum/signature check of FIT images in SPL > - Use of dcache to speed up checksum check in SPL > - SDMA use for eMMC access to speed up read/write in U-Boot proper > > Changes that would be good for future: > - Include and use pinctrl in SPL Yes > - Use dm gpio instead of spl_gpio functions in SPL Where are you looking for spl_gpio? I'm not seeing it. > > I do not have any bob or kevin so this has only been compile tested. > > This should be broken down into smaller logical patches if this is > accepted and works on real hardware. I forgot that I broke my bob and need to fix it. For kevin (which is very similar): before: 06:57 $ ub-int kevin Building U-Boot in sourcedir for chromebook_kevin Bootstrapping U-Boot from dir /tmp/b/chromebook_kevin Writing U-Boot using method em100 Channel 0: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride U-Boot SPL 2024.07-rc4-00009-g0ae095f4664 (Aug 01 2024 - 06:57:12 -0600) Bloblist at 100000 not found (err=-2) Trying to boot from SPI ns16550_serial serial@ff1a0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 U-Boot 2024.07-rc4-00009-g0ae095f4664 (Aug 01 2024 - 06:57:12 -0600) Model: Google Kevin DRAM: 4 GiB (effective 3.9 GiB) Core: 329 devices, 33 uclasses, devicetree: separate MMC: mmc@fe320000: 1, mmc@fe330000: 0 Loading Environment from MMC... Reading from MMC(0)... *** Warning - bad CRC, using default environment edp_rockchip dp@ff970000: failed to set rate on clock index 0 (362) (error = -2) edp_rockchip dp@ff970000: failed to set rate on clock index 0 (362) (error = -2) In: serial,cros-ec-keyb Out: serial,vidconsole Err: serial,vidconsole Model: Google Kevin Net: No ethernet found. Hit any key to stop autoboot: 0 => with your patch: 06:53 $ ub-int kevin Building U-Boot in sourcedir for chromebook_kevin Bootstrapping U-Boot from dir /tmp/b/chromebook_kevin Writing U-Boot using method em100 U-Boot SPL 2024.07-rc4-00010-g14d97804e94 (Aug 01 2024 - 06:53:17 -0600) Checksum 0 != 68 Bloblist at 100000 not found (err=-5) Trying to boot from SPI ## Checking hash(es) for config conf-1 ... OK ## Checking hash(es) for Image firmware-1 ... crc32+ OK ## Checking hash(es) for Image fdt-1 ... crc32+ OK ns16550_serial serial@ff1a0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 U-Boot 2024.07-rc4-00010-g14d97804e94 (Aug 01 2024 - 06:53:17 -0600) Model: Google Kevin DRAM: 4 GiB (effective 3.9 GiB) Core: 330 devices, 34 uclasses, devicetree: separate MMC: mmc@fe320000: 1, mmc@fe330000: 0 Loading Environment from MMC... Reading from MMC(0)... *** Warning - bad CRC, using default environment edp_rockchip dp@ff970000: failed to set rate on clock index 0 (362) (error = -2) edp_rockchip dp@ff970000: failed to set rate on clock index 0 (362) (error = -2) In: serial,cros-ec-keyb Out: serial,vidconsole Err: serial,vidconsole Model: Google Kevin Net: No ethernet found. Hit any key to stop autoboot: 0 => Regards, SImon
Hi Simon, On 2024-08-01 15:07, Simon Glass wrote: > Hi Jonas, > > On Thu, 1 Aug 2024 at 02:37, Jonas Karlman <jonas@kwiboo.se> wrote: >> >> All Rockchip aarch64 boards, beside bob and kevin, use TPL to initialize >> DRAM and SPL to load FIT with U-Boot proper and TF-A. >> >> Bob and kevin currently does not use TPL and instead initialize DRAM >> in SPL and directly after tries to load FIT with U-Boot proper and TF-A. >> >> This RFC try to migrate bob and kevin to also use TPL to uniform TPL/SPL >> use for all Rockchip aarch64 boards. > > Thanks for doing this! > >> >> Notes and questions: >> - Is u-boot.rom even used for bob/kevin? It use u-boot-img, yet SPL >> expect to load FIT and does not permit use of raw imgage. > > Yes it does use u-boot.rom > >> >> Q: Can we remove what looks to be a faulty u-boot.rom definition and >> just use u-boot-rockchip-spi.bin instead? > > Maybe, but we do need the image to be the correct size. Maybe just changing the u-boot-img to something like following could possible work for the u-boot.rom output? fit { type = "blob"; filename = "u-boot.itb"; offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; }; Similar to how it is done for the u-boot-rockchip-spi.bin output. > >> >> - FIT location moved from 0x40000 to 0xE0000 in SPI flash to allow for a >> larger SPL, up to 256 KiB, same as on other RK3399 boards. >> >> Q: Can we use this location?, or is there something external that >> expects fit or u-boot-img at this location? > > It should be fine. > >> >> Features that is now used: >> - Use of Rockchip aarch64 common bss and stack addresses >> - Checksum/signature check of FIT images in SPL >> - Use of dcache to speed up checksum check in SPL >> - SDMA use for eMMC access to speed up read/write in U-Boot proper >> >> Changes that would be good for future: >> - Include and use pinctrl in SPL > > Yes Looks like the pinctrl driver is already include in SPL, so we probably only need to include the pinctrl-0 props and pinctrl nodes in SPL FDT. Should help fix some of the pinctrl_select_state_full errors seen in your output log below. > >> - Use dm gpio instead of spl_gpio functions in SPL > > Where are you looking for spl_gpio? I'm not seeing it. board_debug_uart_init() in rk3399.c contains some special code for bob and kevin using spl_gpio_output() and spl_gpio_set_pull(). led_setup() in roc-pc-rk3399.c is the only other user of these functions, so would be nice if we can remove them and use full dm_gpio variants instead. Something for a separate series. > >> >> I do not have any bob or kevin so this has only been compile tested. >> >> This should be broken down into smaller logical patches if this is >> accepted and works on real hardware. > > I forgot that I broke my bob and need to fix it. For kevin (which is > very similar): > > before: > 06:57 $ ub-int kevin > Building U-Boot in sourcedir for chromebook_kevin > Bootstrapping U-Boot from dir /tmp/b/chromebook_kevin > Writing U-Boot using method em100 > Channel 0: LPDDR3, 933MHz > BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB > Channel 1: LPDDR3, 933MHz > BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB > 256B stride > > U-Boot SPL 2024.07-rc4-00009-g0ae095f4664 (Aug 01 2024 - 06:57:12 -0600) > Bloblist at 100000 not found (err=-2) > Trying to boot from SPI > ns16550_serial serial@ff1a0000: pinctrl_select_state_full: > uclass_get_device_by_phandle_id: err=-19 > > > U-Boot 2024.07-rc4-00009-g0ae095f4664 (Aug 01 2024 - 06:57:12 -0600) > > Model: Google Kevin > DRAM: 4 GiB (effective 3.9 GiB) > Core: 329 devices, 33 uclasses, devicetree: separate > MMC: mmc@fe320000: 1, mmc@fe330000: 0 > Loading Environment from MMC... Reading from MMC(0)... *** Warning - > bad CRC, using default environment > > edp_rockchip dp@ff970000: failed to set rate on clock index 0 (362) (error = -2) > edp_rockchip dp@ff970000: failed to set rate on clock index 0 (362) (error = -2) > In: serial,cros-ec-keyb > Out: serial,vidconsole > Err: serial,vidconsole > Model: Google Kevin > Net: No ethernet found. > > Hit any key to stop autoboot: 0 > => > > with your patch: > 06:53 $ ub-int kevin > Building U-Boot in sourcedir for chromebook_kevin > Bootstrapping U-Boot from dir /tmp/b/chromebook_kevin > Writing U-Boot using method em100 > > U-Boot SPL 2024.07-rc4-00010-g14d97804e94 (Aug 01 2024 - 06:53:17 -0600) > Checksum 0 != 68 > Bloblist at 100000 not found (err=-5) > Trying to boot from SPI > ## Checking hash(es) for config conf-1 ... OK > ## Checking hash(es) for Image firmware-1 ... crc32+ OK > ## Checking hash(es) for Image fdt-1 ... crc32+ OK > ns16550_serial serial@ff1a0000: pinctrl_select_state_full: > uclass_get_device_by_phandle_id: err=-19 > > > U-Boot 2024.07-rc4-00010-g14d97804e94 (Aug 01 2024 - 06:53:17 -0600) > > Model: Google Kevin > DRAM: 4 GiB (effective 3.9 GiB) > Core: 330 devices, 34 uclasses, devicetree: separate > MMC: mmc@fe320000: 1, mmc@fe330000: 0 > Loading Environment from MMC... Reading from MMC(0)... *** Warning - > bad CRC, using default environment > > edp_rockchip dp@ff970000: failed to set rate on clock index 0 (362) (error = -2) > edp_rockchip dp@ff970000: failed to set rate on clock index 0 (362) (error = -2) > In: serial,cros-ec-keyb > Out: serial,vidconsole > Err: serial,vidconsole > Model: Google Kevin > Net: No ethernet found. > > Hit any key to stop autoboot: 0 > => Thanks for testing! I am guessing the output from TPL was just not captured or could there be an issue with debug uart/serial in TPL? Also the FIT image names and hash method does not match the ones defined for binman image in rockchip-u-boot.dtsi, are you building a custom FIT? I will split into logical smaller patches and send a series later. Regards, Jonas > > Regards, > SImon
diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index 6bdc892bd913..1d43e07091f4 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -11,7 +11,7 @@ }; config { - u-boot,spl-payload-offset = <0x40000>; + u-boot,spl-payload-offset = <0xE0000>; }; }; @@ -80,7 +80,8 @@ &spi1 { spi_flash: flash@0 { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; }; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 2bec139d8338..cb64c5fc3d4b 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -39,11 +39,19 @@ mkimage { args = "-n rk3399 -T rkspi"; + multiple-data-files; +#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL + rockchip-tpl { + }; +#elif defined(CONFIG_TPL) + u-boot-tpl { + }; +#endif u-boot-spl { }; }; u-boot-img { - offset = <0x40000>; + offset = <0xE0000>; }; u-boot { offset = <0x300000>; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index fc1b638ff01d..c0a8bd929dd7 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -289,6 +289,7 @@ config ROCKCHIP_RK3399 imply SPL_FIT_SIGNATURE imply SPL_ROCKCHIP_COMMON_BOARD imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT + imply TPL if !ROCKCHIP_EXTERNAL_TPL imply TPL_CLK imply TPL_DM imply TPL_LIBCOMMON_SUPPORT diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 04a84e2f6a04..500cfcd87afd 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -146,15 +146,6 @@ config SYS_SOC config ROCKCHIP_COMMON_STACK_ADDR default y -config SYS_MALLOC_F_LEN - default 0x4000 if !SPL_SHARES_INIT_SP_ADDR - -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT - default y - config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" @@ -164,9 +155,6 @@ config TPL_STACK config TPL_TEXT_BASE default 0xff8c2000 -config SPL_STACK_R_ADDR - default 0x04000000 if !SPL_SHARES_INIT_SP_ADDR - if BOOTCOUNT_LIMIT config BOOTCOUNT_BOOTLIMIT diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 2d7d0f82a2f1..3b6a9c7951a6 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -136,7 +136,7 @@ void board_debug_uart_init(void) struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; - if (IS_ENABLED(CONFIG_SPL_BUILD) && + if (IS_ENABLED(CONFIG_SPL_BUILD) && !IS_ENABLED(CONFIG_TPL_BUILD) && (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) || IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) { rk_setreg(&grf->io_vsel, 1 << 0); diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index b2ecfa6050c8..65854389789a 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -1,35 +1,22 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-bob" -CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 # CONFIG_SPL_MMC is not set -CONFIG_SPL_STACK=0xff8effff -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_DEBUG_UART_BASE=0xff1a0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y -# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -37,14 +24,14 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x1e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -75,6 +62,7 @@ CONFIG_MMC_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_GIGADEVICE=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 0fba5912e0e7..2f3ffb3db46c 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -1,36 +1,23 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-kevin" -CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 # CONFIG_SPL_MMC is not set CONFIG_TARGET_CHROMEBOOK_KEVIN=y -CONFIG_SPL_STACK=0xff8effff -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_DEBUG_UART_BASE=0xff1a0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y -# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -38,14 +25,14 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x1e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -76,6 +63,7 @@ CONFIG_MMC_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_GIGADEVICE=y
All Rockchip aarch64 boards, beside bob and kevin, use TPL to initialize DRAM and SPL to load FIT with U-Boot proper and TF-A. Bob and kevin currently does not use TPL and instead initialize DRAM in SPL and directly after tries to load FIT with U-Boot proper and TF-A. This RFC try to migrate bob and kevin to also use TPL to uniform TPL/SPL use for all Rockchip aarch64 boards. Notes and questions: - Is u-boot.rom even used for bob/kevin? It use u-boot-img, yet SPL expect to load FIT and does not permit use of raw imgage. Q: Can we remove what looks to be a faulty u-boot.rom definition and just use u-boot-rockchip-spi.bin instead? - FIT location moved from 0x40000 to 0xE0000 in SPI flash to allow for a larger SPL, up to 256 KiB, same as on other RK3399 boards. Q: Can we use this location?, or is there something external that expects fit or u-boot-img at this location? Features that is now used: - Use of Rockchip aarch64 common bss and stack addresses - Checksum/signature check of FIT images in SPL - Use of dcache to speed up checksum check in SPL - SDMA use for eMMC access to speed up read/write in U-Boot proper Changes that would be good for future: - Include and use pinctrl in SPL - Use dm gpio instead of spl_gpio functions in SPL I do not have any bob or kevin so this has only been compile tested. This should be broken down into smaller logical patches if this is accepted and works on real hardware. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> --- arch/arm/dts/rk3399-gru-u-boot.dtsi | 5 +++-- arch/arm/dts/rk3399-u-boot.dtsi | 10 +++++++++- arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/rk3399/Kconfig | 12 ------------ arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +- configs/chromebook_bob_defconfig | 20 ++++---------------- configs/chromebook_kevin_defconfig | 20 ++++---------------- 7 files changed, 22 insertions(+), 48 deletions(-)