diff mbox series

[PATCHv2] clk: imx8m: register ARM A53 core clock

Message ID 20240726102954.14546-1-Zhiqiang.Hou@nxp.com
State Superseded
Delegated to: Fabio Estevam
Headers show
Series [PATCHv2] clk: imx8m: register ARM A53 core clock | expand

Commit Message

Z.Q. Hou July 26, 2024, 10:29 a.m. UTC
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - Fixed the change log: s/A55/A53

 drivers/clk/imx/clk-imx8mm.c | 6 ++++++
 drivers/clk/imx/clk-imx8mn.c | 7 +++++++
 drivers/clk/imx/clk-imx8mp.c | 7 +++++++
 3 files changed, 20 insertions(+)

Comments

Marek Vasut July 26, 2024, 2:05 p.m. UTC | #1
On 7/26/24 12:29 PM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus.

Why is MX8M(Q) not included here ?
Z.Q. Hou July 26, 2024, 4:01 p.m. UTC | #2
Hi Marek,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Friday, July 26, 2024 10:05 PM
> To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de;
> trini@konsulko.com; lukma@denx.de; seanga2@gmail.com;
> festevam@gmail.com; Peng Fan <peng.fan@nxp.com>
> Subject: Re: [PATCHv2] clk: imx8m: register ARM A53 core clock
> 
> On 7/26/24 12:29 PM, Zhiqiang Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus.
> 
> Why is MX8M(Q) not included here ?

I don't know iMX8MQ and it's not in my work plan.

Thanks,
Zhiqiang
Marek Vasut July 26, 2024, 8:38 p.m. UTC | #3
On 7/26/24 6:01 PM, Z.Q. Hou wrote:
> Hi Marek,

Hi,

>> -----Original Message-----
>> From: Marek Vasut <marex@denx.de>
>> Sent: Friday, July 26, 2024 10:05 PM
>> To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de;
>> trini@konsulko.com; lukma@denx.de; seanga2@gmail.com;
>> festevam@gmail.com; Peng Fan <peng.fan@nxp.com>
>> Subject: Re: [PATCHv2] clk: imx8m: register ARM A53 core clock
>>
>> On 7/26/24 12:29 PM, Zhiqiang Hou wrote:
>>> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>>>
>>> Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus.
>>
>> Why is MX8M(Q) not included here ?
> 
> I don't know iMX8MQ and it's not in my work plan.

Uh ... why are you adding this patch in the first place ?

Is there anything (driver? arch code?) which requires these clock ?

MX8M(Q) is very similar to the rest of the MX8M from the software 
perspective, also up to quad-A53.
Fabio Estevam July 27, 2024, 4:42 p.m. UTC | #4
Hi Zhiqiang,

On Fri, Jul 26, 2024 at 5:38 PM Marek Vasut <marex@denx.de> wrote:

> Uh ... why are you adding this patch in the first place ?
>
> Is there anything (driver? arch code?) which requires these clock ?

Marek brings up a good point.

Please explain the motivation/reason for this change in the commit log.

Thanks
Z.Q. Hou July 29, 2024, 2:58 a.m. UTC | #5
Hi Marek,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Saturday, July 27, 2024 4:38 AM
> To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de;
> trini@konsulko.com; lukma@denx.de; seanga2@gmail.com;
> festevam@gmail.com; Peng Fan <peng.fan@nxp.com>
> Subject: Re: [PATCHv2] clk: imx8m: register ARM A53 core clock
> 
> On 7/26/24 6:01 PM, Z.Q. Hou wrote:
> > Hi Marek,
> 
> Hi,
> 
> >> -----Original Message-----
> >> From: Marek Vasut <marex@denx.de>
> >> Sent: Friday, July 26, 2024 10:05 PM
> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de;
> >> trini@konsulko.com; lukma@denx.de; seanga2@gmail.com;
> >> festevam@gmail.com; Peng Fan <peng.fan@nxp.com>
> >> Subject: Re: [PATCHv2] clk: imx8m: register ARM A53 core clock
> >>
> >> On 7/26/24 12:29 PM, Zhiqiang Hou wrote:
> >>> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >>>
> >>> Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus.
> >>
> >> Why is MX8M(Q) not included here ?
> >
> > I don't know iMX8MQ and it's not in my work plan.
> 
> Uh ... why are you adding this patch in the first place ?
> 
> Is there anything (driver? arch code?) which requires these clock ?

Yes, the cmd/cpu.c needs this to print the core frequency. The following patch enables the CONFIG_CPU feature:
http://patchwork.ozlabs.org/project/uboot/patch/20240726175108.34704-12-Zhiqiang.Hou@nxp.com/ 

> 
> MX8M(Q) is very similar to the rest of the MX8M from the software
> perspective, also up to quad-A53.

will have a look, but I'don't have a iMX8MQ board to verify the code.

Thanks,
Zhiqiang
Z.Q. Hou July 29, 2024, 3:14 a.m. UTC | #6
Hi Fabio,

> -----Original Message-----
> From: Fabio Estevam <festevam@gmail.com>
> Sent: Sunday, July 28, 2024 12:43 AM
> To: Marek Vasut <marex@denx.de>; Z.Q. Hou <zhiqiang.hou@nxp.com>
> Cc: u-boot@lists.denx.de; trini@konsulko.com; lukma@denx.de;
> seanga2@gmail.com; Peng Fan <peng.fan@nxp.com>
> Subject: Re: [PATCHv2] clk: imx8m: register ARM A53 core clock
> 
> Hi Zhiqiang,
> 
> On Fri, Jul 26, 2024 at 5:38 PM Marek Vasut <marex@denx.de> wrote:
> 
> > Uh ... why are you adding this patch in the first place ?
> >
> > Is there anything (driver? arch code?) which requires these clock ?
> 
> Marek brings up a good point.
> 
> Please explain the motivation/reason for this change in the commit log.

It's needed by the cmd/cpu.c to print the CPU frequency. will add in next version. Thanks!

Zhiqiang
Fabio Estevam July 29, 2024, 9:12 p.m. UTC | #7
Hi Zhiqiang,

On Mon, Jul 29, 2024 at 12:15 AM Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:

> It's needed by the cmd/cpu.c to print the CPU frequency. will add in next version. Thanks!

Please make this patch part of the cmd/cpu.c series and explain the
rationale in the commit log.

Thanks
Z.Q. Hou July 30, 2024, 2:04 a.m. UTC | #8
Hi Fabio,

> -----Original Message-----
> From: Fabio Estevam <festevam@gmail.com>
> Sent: Tuesday, July 30, 2024 5:13 AM
> To: Z.Q. Hou <zhiqiang.hou@nxp.com>
> Cc: Marek Vasut <marex@denx.de>; u-boot@lists.denx.de;
> trini@konsulko.com; lukma@denx.de; seanga2@gmail.com; Peng Fan
> <peng.fan@nxp.com>
> Subject: Re: [PATCHv2] clk: imx8m: register ARM A53 core clock
> 
> Hi Zhiqiang,
> 
> On Mon, Jul 29, 2024 at 12:15 AM Z.Q. Hou <zhiqiang.hou@nxp.com> wrote:
> 
> > It's needed by the cmd/cpu.c to print the CPU frequency. will add in next
> version. Thanks!
> 
> Please make this patch part of the cmd/cpu.c series and explain the rationale
> in the commit log.

OK, will move it to that series.

Thanks
Zhiqiang
Z.Q. Hou July 30, 2024, 7:02 a.m. UTC | #9
Hi Marek,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Saturday, July 27, 2024 4:38 AM
> To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de;
> trini@konsulko.com; lukma@denx.de; seanga2@gmail.com;
> festevam@gmail.com; Peng Fan <peng.fan@nxp.com>
> Subject: Re: [PATCHv2] clk: imx8m: register ARM A53 core clock
> 
> On 7/26/24 6:01 PM, Z.Q. Hou wrote:
> > Hi Marek,
> 
> Hi,
> 
> >> -----Original Message-----
> >> From: Marek Vasut <marex@denx.de>
> >> Sent: Friday, July 26, 2024 10:05 PM
> >> To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de;
> >> trini@konsulko.com; lukma@denx.de; seanga2@gmail.com;
> >> festevam@gmail.com; Peng Fan <peng.fan@nxp.com>
> >> Subject: Re: [PATCHv2] clk: imx8m: register ARM A53 core clock
> >>
> >> On 7/26/24 12:29 PM, Zhiqiang Hou wrote:
> >>> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >>>
> >>> Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus.
> >>
> >> Why is MX8M(Q) not included here ?
> >
> > I don't know iMX8MQ and it's not in my work plan.
> 
> Uh ... why are you adding this patch in the first place ?
> 
> Is there anything (driver? arch code?) which requires these clock ?
> 
> MX8M(Q) is very similar to the rest of the MX8M from the software
> perspective, also up to quad-A53.

The iMX8MQ clock driver has registered the A53 core clock.

Thanks,
Zhiqiang
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index e538f047b3..8d98fbaaa9 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -21,6 +21,8 @@  static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_se
 static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
 static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
 
+static const char * const imx8mm_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
+
 static const char * const imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
 					       "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
 					       "audio_pll1_out", "sys_pll3_out", };
@@ -417,6 +419,10 @@  static int imx8mm_clk_probe(struct udevice *dev)
 	       imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
 #endif
 
+	clk_dm(IMX8MM_CLK_ARM,
+	       imx_clk_mux2("arm_core", base + 0x9880, 24, 1,
+			    imx8mm_arm_core_sels,
+			    ARRAY_SIZE(imx8mm_arm_core_sels)));
 	return 0;
 }
 
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 8911e342f1..3de03e1f3b 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -23,6 +23,8 @@  static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_se
 static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
 static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
 
+static const char * const imx8mn_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
+
 static const char * const imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
 					       "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
 					       "audio_pll1_out", "sys_pll3_out", };
@@ -403,6 +405,11 @@  static int imx8mn_clk_probe(struct udevice *dev)
 	       imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
 #endif
 
+	clk_dm(IMX8MN_CLK_ARM,
+	       imx_clk_mux2("arm_core", base + 0x9880, 24, 1,
+			    imx8mn_arm_core_sels,
+			    ARRAY_SIZE(imx8mn_arm_core_sels)));
+
 	return 0;
 }
 
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 6b18483c81..32ea60f11e 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -21,6 +21,8 @@  static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_se
 static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
 static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
 
+static const char * const imx8mp_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
+
 static const char * const imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
 					       "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
 					       "audio_pll1_out", "sys_pll3_out", };
@@ -354,6 +356,11 @@  static int imx8mp_clk_probe(struct udevice *dev)
 
 	clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
 
+	clk_dm(IMX8MP_CLK_ARM,
+	       imx_clk_mux2("arm_core", base + 0x9880, 24, 1,
+			    imx8mp_arm_core_sels,
+			    ARRAY_SIZE(imx8mp_arm_core_sels)));
+
 	return 0;
 }