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Wed, 24 Jul 2024 08:48:17 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427f93aabdasm33633015e9.36.2024.07.24.08.48.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jul 2024 08:48:17 -0700 (PDT) From: Neil Armstrong Date: Wed, 24 Jul 2024 17:48:10 +0200 Subject: [PATCH v2 2/3] usb: dwc3: fix dcache flush range calculation MIME-Version: 1.0 Message-Id: <20240724-u-boot-dwc3-gadget-dcache-fixup-v2-2-65836d699a71@linaro.org> References: <20240724-u-boot-dwc3-gadget-dcache-fixup-v2-0-65836d699a71@linaro.org> In-Reply-To: <20240724-u-boot-dwc3-gadget-dcache-fixup-v2-0-65836d699a71@linaro.org> To: Marek Vasut , Tom Rini , Lukasz Majewski , Mattijs Korpershoek Cc: Caleb Connolly , u-boot-qcom@groups.io, u-boot@lists.denx.de, Neil Armstrong X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1172; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=srY3udycfvqYMAFtZZ11qUpBrqT3tgodDPaWL7DnMTs=; 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This causes operation failures Qualcomm platforms. Take in account the alignment and size of the buffer and also flush the previous and last cacheline. Reviewed-by: Mattijs Korpershoek Signed-off-by: Neil Armstrong --- drivers/usb/dwc3/io.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h index 04791d4c9be..1aaf5413c6d 100644 --- a/drivers/usb/dwc3/io.h +++ b/drivers/usb/dwc3/io.h @@ -50,6 +50,9 @@ static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value) static inline void dwc3_flush_cache(uintptr_t addr, int length) { - flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE)); + uintptr_t start_addr = (uintptr_t)addr & ~(ARCH_DMA_MINALIGN - 1); + uintptr_t end_addr = ALIGN((uintptr_t)addr + length, ARCH_DMA_MINALIGN); + + flush_dcache_range(start_addr, end_addr); } #endif /* __DRIVERS_USB_DWC3_IO_H */