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Fri, 5 Jul 2024 11:49:48 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 5 Jul 2024 11:49:47 -0500 Received: from dhruva.dhcp.ti.com (dhruva.dhcp.ti.com [172.24.227.68]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 465Gmhd4028675; Fri, 5 Jul 2024 11:49:43 -0500 From: Dhruva Gole To: Tom Rini CC: , Neha Malcom Francis , Nishant Menon , , , , Robert Nelson , Vibhore Vardhan , Vishal Mahaveer , Sebin Francis , Wadim Egorov , , , Daniel Schultz , Dhruva Gole Subject: [PATCH V5 5/6] doc: ti: am62*: Mention TIFS Stub in img fmts and boot flow Date: Fri, 5 Jul 2024 22:18:32 +0530 Message-ID: <20240705164833.2386549-6-d-gole@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240705164833.2386549-1-d-gole@ti.com> References: <20240705164833.2386549-1-d-gole@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Since AM62x, AM62P and AM62A all use similar boot flows and their low power mode s/w ARCH is also similar in the way that they make use of the TIFS Stub, update their documentation to show where TIFS Stub is. Signed-off-by: Dhruva Gole --- doc/board/ti/am62ax_sk.rst | 4 ++-- doc/board/ti/am62px_sk.rst | 4 ++-- doc/board/ti/am62x_sk.rst | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/doc/board/ti/am62ax_sk.rst b/doc/board/ti/am62ax_sk.rst index 60726b6652ce..92da6f65f9d5 100644 --- a/doc/board/ti/am62ax_sk.rst +++ b/doc/board/ti/am62ax_sk.rst @@ -47,7 +47,7 @@ Boot Flow: ---------- Below is the pictorial representation of boot flow: -.. image:: img/boot_diagram_k3_current.svg +.. image:: img/boot_diagram_am62.svg :alt: Boot flow diagram - Here TIFS acts as master and provides all the critical services. R5/A53 @@ -144,7 +144,7 @@ Image formats: - tispl.bin -.. image:: img/dm_tispl.bin.svg +.. image:: img/tifsstub_dm_tispl.bin.svg :alt: tispl.bin image format Switch Setting for Boot Mode diff --git a/doc/board/ti/am62px_sk.rst b/doc/board/ti/am62px_sk.rst index c80b50681176..3396aae471c6 100644 --- a/doc/board/ti/am62px_sk.rst +++ b/doc/board/ti/am62px_sk.rst @@ -55,7 +55,7 @@ Boot Flow: The bootflow is exactly the same as all SoCs in the am62xxx extended SoC family. Below is the pictorial representation: -.. image:: img/boot_diagram_k3_current.svg +.. image:: img/boot_diagram_am62.svg :alt: Boot flow diagram - Here TIFS acts as master and provides all the critical services. R5/A53 @@ -153,7 +153,7 @@ Image formats: - tispl.bin -.. image:: img/dm_tispl.bin.svg +.. image:: img/tifsstub_dm_tispl.bin.svg :alt: tispl.bin image format OSPI: diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst index 2a25e84f6c97..68ddd2ac94ff 100644 --- a/doc/board/ti/am62x_sk.rst +++ b/doc/board/ti/am62x_sk.rst @@ -46,7 +46,7 @@ Boot Flow: ---------- Below is the pictorial representation of boot flow: -.. image:: img/boot_diagram_k3_current.svg +.. image:: img/boot_diagram_am62.svg :alt: Boot flow diagram - Here TIFS acts as master and provides all the critical services. R5/A53 @@ -161,7 +161,7 @@ Image formats: - tispl.bin -.. image:: img/dm_tispl.bin.svg +.. image:: img/tifsstub_dm_tispl.bin.svg :alt: tispl.bin image format OSPI: