Message ID | 20240702065351.289968-2-l.rubusch@gmail.com |
---|---|
State | New |
Delegated to: | TIEN FONG CHEE |
Headers | show
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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-58613815e1csm5320954a12.44.2024.07.01.23.54.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jul 2024 23:54:24 -0700 (PDT) From: Lothar Rubusch <l.rubusch@gmail.com> To: marex@denx.de, simon.k.r.goldschmidt@gmail.com, tien.fong.chee@intel.com, trini@konsulko.com, sjg@chromium.org, ilias.apalodimas@linaro.org, xypron.glpk@gmx.de Cc: u-boot@lists.denx.de, l.rubusch@gmail.com Subject: [PATCH] ARM: socfpga: show broken function call for arria10 Date: Tue, 2 Jul 2024 06:53:51 +0000 Message-Id: <20240702065351.289968-2-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240702065351.289968-1-l.rubusch@gmail.com> References: <20240702065351.289968-1-l.rubusch@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Tue, 02 Jul 2024 15:00:15 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Unsubscribe: <https://lists.denx.de/options/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> List-Archive: <https://lists.denx.de/pipermail/u-boot/> List-Post: <mailto:u-boot@lists.denx.de> List-Help: <mailto:u-boot-request@lists.denx.de?subject=help> List-Subscribe: <https://lists.denx.de/listinfo/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=subscribe> Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de> X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean |
Series |
ARM: socfpga: show broken function call for arria10
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diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 6d27deeb..c7321bab 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -61,6 +61,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_DESIGNWARE_APB_TIMER=y
This patch only shows the problem on an existing platform. Turning on the cadence QSPI flash breaks the build for arria10. Can you reproduce? make socfpga_arria10_defconfig make Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com> --- NB: Don't apply this config/patch permanently! The Cadence QSPI flash can be tricky due to a write reset register instruction which can brick the board if interrupted. We experienced this situation. So, that's why I removed the config option in my boards (to be upstreamed soon). Hence, my boards won't show the above problem anymore. Anyway, I think the code section in misc_arria10.c have a bug. So, I presented the before patch. --- configs/socfpga_arria10_defconfig | 1 + 1 file changed, 1 insertion(+)