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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4256b097bd6sm46275635e9.30.2024.06.28.10.41.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jun 2024 10:41:38 -0700 (PDT) From: Christian Marangi To: Lukasz Majewski , Sean Anderson , Ryder Lee , Weijie Gao , Chunfeng Yun , GSS_MTK_Uboot_upstream , Tom Rini , u-boot@lists.denx.de, John Crispin Cc: Christian Marangi Subject: [PATCH 04/12] clk: mediatek: add support for gate ID at offset Date: Fri, 28 Jun 2024 19:40:49 +0200 Message-ID: <20240628174114.8675-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240628174114.8675-1-ansuelsmth@gmail.com> References: <20240628174114.8675-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add support to clk_gate ops to reference the clk ID at an offset by using the just introduced gates_offs value from the unified muxes + gates implementation. Gate clock that doesn't have gates_offs set won't be affected as the offset will simply be 0 and won't be offset of any value. Signed-off-by: Christian Marangi --- drivers/clk/mediatek/clk-mtk.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index c3c50f4c14b..79230fc26e0 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -529,8 +529,12 @@ static int mtk_gate_enable(void __iomem *base, const struct mtk_gate *gate) static int mtk_clk_gate_enable(struct clk *clk) { struct mtk_cg_priv *priv = dev_get_priv(clk->dev); - const struct mtk_gate *gate = &priv->gates[clk->id]; + const struct mtk_gate *gate; + + if (clk->id < priv->tree->gates_offs) + return -EINVAL; + gate = &priv->gates[clk->id - priv->tree->gates_offs]; return mtk_gate_enable(priv->base, gate); } @@ -575,8 +579,12 @@ static int mtk_gate_disable(void __iomem *base, const struct mtk_gate *gate) static int mtk_clk_gate_disable(struct clk *clk) { struct mtk_cg_priv *priv = dev_get_priv(clk->dev); - const struct mtk_gate *gate = &priv->gates[clk->id]; + const struct mtk_gate *gate; + if (clk->id < priv->tree->gates_offs) + return -EINVAL; + + gate = &priv->gates[clk->id - priv->tree->gates_offs]; return mtk_gate_disable(priv->base, gate); } @@ -596,8 +604,12 @@ static int mtk_clk_infrasys_disable(struct clk *clk) static ulong mtk_clk_gate_get_rate(struct clk *clk) { struct mtk_cg_priv *priv = dev_get_priv(clk->dev); - const struct mtk_gate *gate = &priv->gates[clk->id]; + const struct mtk_gate *gate; + + if (clk->id < priv->tree->gates_offs) + return -EINVAL; + gate = &priv->gates[clk->id - priv->tree->gates_offs]; /* * Assume xtal_rate to be declared if some gates have * XTAL as parent