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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id a640c23a62f3a-a6f56f416dfsm60580366b.164.2024.06.13.04.10.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jun 2024 04:10:26 -0700 (PDT) From: Christian Marangi To: Tom Rini , Lukasz Majewski , Sean Anderson , Ryder Lee , Weijie Gao , Chunfeng Yun , GSS_MTK_Uboot_upstream , Heiko Schocher , Peng Fan , Jaehoon Chung , Joe Hershberger , Ramon Fried , Jagan Teki , Bin Meng , Sergei Antonov , Leo Yu-Chi Liang , Simon Glass , Christian Marangi , Mayuresh Chitale , Mason Huo , Mark Kettenis , Sumit Garg , John Crispin , Heinrich Schuchardt , Minda Chen , Marek Vasut , This contributor prefers not to receive mails , Stefan Roese , Peter Robinson , Sam Shih , u-boot@lists.denx.de Subject: [PATCH v2 08/14] mmc: mediatek: add support for upstream linux clock and property Date: Thu, 13 Jun 2024 13:09:26 +0200 Message-ID: <20240613110949.11076-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240613110949.11076-1-ansuelsmth@gmail.com> References: <20240613110949.11076-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 13 Jun 2024 14:43:53 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add support for upstream linux clock and map U-Boot property to the one use in upstream linux where supported. Also add handling for the use_internal_cd that on upstream is hardcoded enabled on mt7620. Signed-off-by: Christian Marangi --- drivers/mmc/mtk-sd.c | 35 +++++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index 296aaee7331..65b6b02e759 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -336,6 +336,7 @@ struct msdc_compatible { bool enhance_rx; bool builtin_pad_ctrl; bool default_pad_dly; + bool use_internal_cd; }; struct msdc_delay_phase { @@ -366,6 +367,10 @@ struct msdc_host { struct clk src_clk_cg; /* optional, MSDC source clock control gate */ struct clk h_clk; /* MSDC core clock */ + /* upstream linux clock */ + struct clk axi_cg_clk; /* optional, AXI clock */ + struct clk ahb_cg_clk; /* optional, AHB clock */ + u32 src_clk_freq; /* source clock */ u32 mclk; /* mmc framework required bus clock */ u32 sclk; /* actual calculated bus clock */ @@ -1638,6 +1643,11 @@ static void msdc_ungate_clock(struct msdc_host *host) clk_enable(&host->h_clk); if (host->src_clk_cg.dev) clk_enable(&host->src_clk_cg); + + if (host->axi_cg_clk.dev) + clk_enable(&host->axi_cg_clk); + if (host->ahb_cg_clk.dev) + clk_enable(&host->ahb_cg_clk); } static int msdc_drv_probe(struct udevice *dev) @@ -1651,6 +1661,9 @@ static int msdc_drv_probe(struct udevice *dev) host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev); + if (host->dev_comp->use_internal_cd) + host->builtin_cd = 1; + host->src_clk_freq = clk_get_rate(&host->src_clk); if (host->dev_comp->clk_div_bits == 8) @@ -1716,18 +1729,31 @@ static int msdc_of_to_plat(struct udevice *dev) clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */ + /* upstream linux clock */ + clk_get_by_name(dev, "axi_cg", &host->axi_cg_clk); /* optional */ + clk_get_by_name(dev, "ahb_cg", &host->ahb_cg_clk); /* optional */ + #if CONFIG_IS_ENABLED(DM_GPIO) gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN); gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN); #endif host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0); - host->hs200_cmd_int_delay = - dev_read_u32_default(dev, "cmd_int_delay", 0); + if (dev_read_u32(dev, "mediatek,hs200-cmd-int-delay", + &host->hs200_cmd_int_delay)) + host->hs200_cmd_int_delay = + dev_read_u32_default(dev, "cmd_int_delay", 0); + host->hs200_write_int_delay = dev_read_u32_default(dev, "write_int_delay", 0); - host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0); + + if (dev_read_u32(dev, "mediatek,latch-ck", &host->latch_ck)) + host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0); + host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0); + if (dev_read_bool(dev, "mediatek,hs400-cmd-resp-sel-rising")) + host->r_smpl = 1; + host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0); host->cd_active_high = dev_read_bool(dev, "cd-active-high"); @@ -1776,6 +1802,7 @@ static const struct msdc_compatible mt7620_compat = { .enhance_rx = false, .builtin_pad_ctrl = true, .default_pad_dly = true, + .use_internal_cd = true, }; static const struct msdc_compatible mt7621_compat = { @@ -1806,7 +1833,7 @@ static const struct msdc_compatible mt7623_compat = { .data_tune = true, .busy_check = false, .stop_clk_fix = false, - .enhance_rx = false + .enhance_rx = false, }; static const struct msdc_compatible mt7986_compat = {