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Mon, 10 Jun 2024 15:34:11 +0200 (CEST) Received: from augenblix2.phytec.de (172.25.0.11) by Berlix.phytec.de (172.25.0.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.6; Mon, 10 Jun 2024 15:34:11 +0200 From: Wadim Egorov To: , , CC: , , Subject: [PATCH 13/13] board: phytec: phycore-am62x: Use memory nodes in higher boot stages Date: Mon, 10 Jun 2024 15:33:52 +0200 Message-ID: <20240610133352.2473414-14-w.egorov@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240610133352.2473414-1-w.egorov@phytec.de> References: <20240610133352.2473414-1-w.egorov@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Berlix.phytec.de (172.25.0.12) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrELMWRmVeSWpSXmKPExsWyRpKBR/cyQ3qaQX+PvMWHxs1sFlMnbWa3 eLu3k93iXd9+Jovud+oOrB6vDqxi9zh7ZwejR393C6vHn4vvWANYorhsUlJzMstSi/TtErgy jk+5wlzwlL/i6J3QBsapvF2MnBwSAiYS36a8Z+1i5OIQEljCJPF3/md2COcxo8SePcuZQKrY BNQl7mz4xgpiiwgESfRe+sQIYjMLeEhs/bsBLC4sEC1x6dFiFhCbRUBV4un3eUC9HBy8AlYS t1eHQCyTl5h56Ts7iM0JFP6xZi9Yq5CApcSiT2vAWnkFBCVOznzCAjFeXqJ562xmCFtC4uCL F8wQ9fISLy4tZ4GZOe3ca2YIO1Ri65ftTBMYhWYhGTULyahZSEYtYGRexSiUm5mcnVqUma1X kFFZkpqsl5K6iREU7iIMXDsY++Z4HGJk4mA8xCjBwawkwiuUkZwmxJuSWFmVWpQfX1Sak1p8 iFGag0VJnHd1R3CqkEB6YklqdmpqQWoRTJaJg1OqgbHay+/WXBfnrsgf2T6zb+qUtbvcTYjd 2b9mUsPKV07zsyIPf2VWDRSXc/jyx26yz+sefwOze0UGN39cyVFesle8Ms3E4d19tcLN9k8n snPZrRaJmq10IIpR+nfe7a1XbkwqqPOf75j6h+WXZnfu91335B/Pm/+58c2au07nd3Foa/zn lVMt6FBiKc5INNRiLipOBADGkirMZQIAAA== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean There is no need to reread the EEPROM multiple times in different stages to detect the RAM size. We can do this once at an early stage and let higher stages decode memory nodes using fdtdec. Make sure to pass fixup memory nodes before passing to u-boot stage. Signed-off-by: Wadim Egorov --- board/phytec/phycore_am62x/phycore-am62x.c | 30 +++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index 35e1bb96b8d..9f6bc736cbb 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -47,7 +47,12 @@ static u8 phytec_get_am62_ddr_size_default(void) int dram_init(void) { - u8 ram_size = phytec_get_am62_ddr_size_default(); + u8 ram_size; + + if (!IS_ENABLED(CONFIG_CPU_V7R)) + return fdtdec_setup_mem_size_base(); + + ram_size = phytec_get_am62_ddr_size_default(); /* * HACK: ddrss driver support 2GB RAM by default @@ -92,6 +97,9 @@ int dram_init_banksize(void) { u8 ram_size; + if (!IS_ENABLED(CONFIG_CPU_V7R)) + return fdtdec_setup_memory_banksize(); + ram_size = phytec_get_am62_ddr_size_default(); switch (ram_size) { case EEPROM_RAM_SIZE_1GB: @@ -174,6 +182,26 @@ int do_board_detect(void) } #endif +#if IS_ENABLED(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int bank; + int ret; + + dram_init(); + dram_init_banksize(); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = gd->bd->bi_dram[bank].start; + size[bank] = gd->bd->bi_dram[bank].size; + } + + ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, CONFIG_NR_DRAM_BANKS); +} +#endif + #define CTRLMMR_USB0_PHY_CTRL 0x43004008 #define CTRLMMR_USB1_PHY_CTRL 0x43004018 #define CORE_VOLTAGE 0x80000000