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[next,v3,6/6] rockchip: ringneck-px30: fix TPL_MAX_SIZE

Message ID 20240606-misc-tsd-v3-6-728d721c464a@cherry.de
State Accepted
Commit 724d3c686c57b3ce50a39dceb3f3f1ebc9d3e32c
Delegated to: Kever Yang
Headers show
Series rockchip: display PMIC variant properly + misc fixes for Theobroma boards | expand

Commit Message

Quentin Schulz June 6, 2024, 8:45 a.m. UTC 
From: Quentin Schulz <quentin.schulz@cherry.de>

Ringneck was mistakenly set to allow up to 128KiB for the TPL code size
while PX30 SoC only has 16KiB of SRAM.

Therefore, let's use the default value of TPL_MAX_SIZE from the SoC
(which is 10KiB) so that the max code size is actually checked and
useful.

Fixes: c925be73a0a8 ("rockchip: add support for PX30 Ringneck SoM on Haikou Devkit")
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
---
 configs/ringneck-px30_defconfig | 1 -
 1 file changed, 1 deletion(-)
diff mbox series

Patch

diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index a22d25e0089..9965e55d611 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -14,7 +14,6 @@  CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_DEBUG_UART_BASE=0xFF030000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0x800800
-CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_FIT=y