| Message ID | 20240528170406.353616-8-liujianfeng1994@gmail.com |
|---|---|
| State | Accepted |
| Commit | 95967c4a7469c24f48d4f9c887ee979c0b5547e7 |
| Delegated to: | Kever Yang |
| Headers | show |
| Series | add ArmSoM Sige7 Rk3588 board | expand |
On 2024/5/29 01:04, Jianfeng Liu wrote: > From: Niklas Cassel <cassel@kernel.org> > > The mmu600_pcie is connected with the five PCIe controllers. > The mmu600_php is connected with the USB3 controller, the GMAC > controllers, and the SATA controllers. > > See 8.2 Block Diagram, in rk3588 TRM (Technical Reference Manual). > > The IOMMUs are disabled by default, as further patches are needed to > program the SID/SSIDs in to the IOMMUs. > > iommu: Default domain type: Translated > iommu: DMA domain TLB invalidation policy: strict mode > arm-smmu-v3 fc900000.iommu: ias 48-bit, oas 48-bit (features 0x001c1eaf) > arm-smmu-v3 fc900000.iommu: allocated 65536 entries for cmdq > arm-smmu-v3 fc900000.iommu: allocated 32768 entries for evtq > arm-smmu-v3 fc900000.iommu: msi_domain absent - falling back to wired irqs > > Additionally, the IOMMU correctly triggers an IOMMU fault when > a PCIe device performs a write (since the device hasn't been > assigned a SID/SSID): > arm-smmu-v3 fc900000.iommu: event 0x02 received: > arm-smmu-v3 fc900000.iommu: 0x0000010000000002 > arm-smmu-v3 fc900000.iommu: 0x0000000000000000 > arm-smmu-v3 fc900000.iommu: 0x0000000000000000 > arm-smmu-v3 fc900000.iommu: 0x0000000000000000 > > While this doesn't provide much value as is, having the devices as > disabled in the device tree will allow developers to see that the rk3588 > actually has IOMMUs on the SoC. > > Signed-off-by: Niklas Cassel <cassel@kernel.org> > Link: https://lore.kernel.org/r/20240502140231.477049-2-cassel@kernel.org > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > > [ upstream commit: cd81d3a0695cc54ad6ac0ef4bbb67a7c8f55d592 ] > > (cherry picked from commit ea9a34aa0d786cbf4b87f1ba528e69b07219738f) > Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Thanks, - Kever > --- > > (no changes since v1) > > dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 24 ++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi > index b0a59ec5183..6ac5ac8b48a 100644 > --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi > +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi > @@ -579,6 +579,30 @@ > status = "disabled"; > }; > > + mmu600_pcie: iommu@fc900000 { > + compatible = "arm,smmu-v3"; > + reg = <0x0 0xfc900000 0x0 0x200000>; > + interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>; > + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; > + #iommu-cells = <1>; > + status = "disabled"; > + }; > + > + mmu600_php: iommu@fcb00000 { > + compatible = "arm,smmu-v3"; > + reg = <0x0 0xfcb00000 0x0 0x200000>; > + interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>, > + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; > + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; > + #iommu-cells = <1>; > + status = "disabled"; > + }; > + > pmu1grf: syscon@fd58a000 { > compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; > reg = <0x0 0xfd58a000 0x0 0x10000>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi index b0a59ec5183..6ac5ac8b48a 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi @@ -579,6 +579,30 @@ status = "disabled"; }; + mmu600_pcie: iommu@fc900000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfc900000 0x0 0x200000>; + interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + + mmu600_php: iommu@fcb00000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfcb00000 0x0 0x200000>; + interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + pmu1grf: syscon@fd58a000 { compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xfd58a000 0x0 0x10000>;