| Message ID | 20240528170406.353616-5-liujianfeng1994@gmail.com |
|---|---|
| State | Accepted |
| Commit | e1a374d5845e26016e7b67b0d531a6536c42b76b |
| Delegated to: | Kever Yang |
| Headers | show |
| Series | add ArmSoM Sige7 Rk3588 board | expand |
On 2024/5/29 01:04, Jianfeng Liu wrote: > From: Sebastian Reichel <sebastian.reichel@collabora.com> > > Reorder common DT properties alphabetically for usb2phy, according > to latest DT style rules. > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > Link: https://lore.kernel.org/r/20240408225109.128953-6-sebastian.reichel@collabora.com > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > > [ upstream commit: abe68e0ca71dddce0e5419e35507cb464d61870d ] > > (cherry picked from commit f6835a60a8a28ff14ffb3dd80c99ce1c137d06c5) > Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Thanks, - Kever > --- > > (no changes since v1) > > dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi > index 87df0902273..58d12969b7e 100644 > --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi > +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi > @@ -602,13 +602,13 @@ > u2phy2: usb2phy@8000 { > compatible = "rockchip,rk3588-usb2phy"; > reg = <0x8000 0x10>; > - interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; > - resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; > - reset-names = "phy", "apb"; > + #clock-cells = <0>; > clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; > clock-names = "phyclk"; > clock-output-names = "usb480m_phy2"; > - #clock-cells = <0>; > + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; > + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; > + reset-names = "phy", "apb"; > status = "disabled"; > > u2phy2_host: host-port { > @@ -627,13 +627,13 @@ > u2phy3: usb2phy@c000 { > compatible = "rockchip,rk3588-usb2phy"; > reg = <0xc000 0x10>; > - interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; > - resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; > - reset-names = "phy", "apb"; > + #clock-cells = <0>; > clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; > clock-names = "phyclk"; > clock-output-names = "usb480m_phy3"; > - #clock-cells = <0>; > + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; > + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; > + reset-names = "phy", "apb"; > status = "disabled"; > > u2phy3_host: host-port {
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi index 87df0902273..58d12969b7e 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi @@ -602,13 +602,13 @@ u2phy2: usb2phy@8000 { compatible = "rockchip,rk3588-usb2phy"; reg = <0x8000 0x10>; - interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; - resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; - reset-names = "phy", "apb"; + #clock-cells = <0>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; clock-names = "phyclk"; clock-output-names = "usb480m_phy2"; - #clock-cells = <0>; + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; + reset-names = "phy", "apb"; status = "disabled"; u2phy2_host: host-port { @@ -627,13 +627,13 @@ u2phy3: usb2phy@c000 { compatible = "rockchip,rk3588-usb2phy"; reg = <0xc000 0x10>; - interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; - resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; - reset-names = "phy", "apb"; + #clock-cells = <0>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; clock-names = "phyclk"; clock-output-names = "usb480m_phy3"; - #clock-cells = <0>; + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; + reset-names = "phy", "apb"; status = "disabled"; u2phy3_host: host-port {