diff mbox series

[1/1] andes: l2 cache driver: fixes typos and cctl status

Message ID 20240528124942.933925-1-ycliang@andestech.com
State Accepted
Commit ceec4761141a920602c4a4c7b90039d144ec2e58
Delegated to: Andes
Headers show
Series [1/1] andes: l2 cache driver: fixes typos and cctl status | expand

Commit Message

Leo Liang May 28, 2024, 12:49 p.m. UTC 
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
 drivers/cache/cache-andes-l2.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/cache/cache-andes-l2.c b/drivers/cache/cache-andes-l2.c
index 45d29f2fbd..bc6f7ed7c1 100644
--- a/drivers/cache/cache-andes-l2.c
+++ b/drivers/cache/cache-andes-l2.c
@@ -30,7 +30,7 @@  struct l2cache {
 	volatile u64	cctl_command2;
 	volatile u64	cctl_access_line2;
 	volatile u64	cctl_command3;
-	volatile u64	cctl_access_line4;
+	volatile u64	cctl_access_line3;
 	volatile u64	cctl_status;
 };
 
@@ -97,13 +97,15 @@  static int andes_l2_disable(struct udevice *dev)
 	struct andes_l2_plat *plat = dev_get_plat(dev);
 	volatile struct l2cache *regs = plat->regs;
 	u8 hart = gd->arch.boot_hart;
+
 	void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
+	void __iomem *cctlstatus = (void __iomem *)CCTL_STATUS_REG(regs, hart);
 
 	if ((regs) && (readl(&regs->control) & L2_ENABLE)) {
 		writel(L2_WBINVAL_ALL, cctlcmd);
 
-		while ((readl(&regs->cctl_status) & CCTL_STATUS_MSK(hart))) {
-			if ((readl(&regs->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
+		while ((readl(cctlstatus) & CCTL_STATUS_MSK(hart))) {
+			if ((readl(cctlstatus) & CCTL_STATUS_ILLEGAL(hart))) {
 				printf("L2 flush illegal! hanging...");
 				hang();
 			}