| Message ID | 20240528124919.933294-1-ycliang@andestech.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | [1/1] andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND | expand |
diff --git a/arch/riscv/cpu/andes/cache.c b/arch/riscv/cpu/andes/cache.c index 7d3df8722d..bb57498d75 100644 --- a/arch/riscv/cpu/andes/cache.c +++ b/arch/riscv/cpu/andes/cache.c @@ -43,9 +43,7 @@ static void cache_ops(int (*ops)(struct udevice *dev)) void flush_dcache_all(void) { -#if CONFIG_IS_ENABLED(RISCV_MMODE) - csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); -#endif + csr_write(CSR_UCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); } void flush_dcache_range(unsigned long start, unsigned long end)
Use CSR_UCCTLCOMMAND instead of CSR_MCCTLCOMMAND to do cache flush operation in M-mode and S-mode. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> --- arch/riscv/cpu/andes/cache.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)