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Busch-George" , Nam Cao Subject: [PATCH] riscv: dts: jh7110: Update qspi node with upstream Date: Mon, 27 May 2024 12:47:10 +0200 Message-ID: <20240527104730.20244-1-matthias.bgg@kernel.org> X-Mailer: git-send-email 2.44.0 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Matthias Brugger Upstream node uses a specific SoC compatible to make the kernel driver work. Copy over the upstream node to fullfill that need. Signed-off-by: Matthias Brugger --- .../jh7110-starfive-visionfive-2-u-boot.dtsi | 2 +- .../dts/jh7110-starfive-visionfive-2.dtsi | 29 ++++++++++++++++--- arch/riscv/dts/jh7110.dtsi | 19 +++++++----- 3 files changed, 37 insertions(+), 13 deletions(-) diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi index 3012466b305..a69d8fcb391 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi @@ -40,7 +40,7 @@ &qspi { bootph-pre-ram; - nor-flash@0 { + nor_flash@0 { bootph-pre-ram; }; }; diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi index e11babc1cde..375449b73a8 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi @@ -305,17 +305,38 @@ }; &qspi { - spi-max-frequency = <250000000>; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; - nor-flash@0 { + nor_flash: nor_flash@0 { compatible = "jedec,spi-nor"; - reg=<0>; - spi-max-frequency = <100000000>; + reg = <0>; + cdns,read-delay = <5>; + spi-max-frequency = <12000000>; cdns,tshsl-ns = <1>; cdns,tsd2d-ns = <1>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + spl@0 { + reg = <0x0 0x80000>; + }; + uboot-env@f0000 { + reg = <0xf0000 0x10000>; + }; + uboot@100000 { + reg = <0x100000 0x400000>; + }; + reserved-data@600000 { + reg = <0x600000 0xa00000>; + }; + }; }; }; diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 2cdc683d49b..2b331e58497 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -480,19 +480,22 @@ }; qspi: spi@13010000 { - compatible = "cdns,qspi-nor"; - reg = <0x0 0x13010000 0x0 0x10000 - 0x0 0x21000000 0x0 0x400000>; - clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>; - clock-names = "clk_ref"; + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; + reg = <0x0 0x13010000 0x0 0x10000>, + <0x0 0x21000000 0x0 0x400000>; + interrupts = <25>; + clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>, + <&syscrg JH7110_SYSCLK_QSPI_AHB>, + <&syscrg JH7110_SYSCLK_QSPI_APB>; + clock-names = "ref", "ahb", "apb"; resets = <&syscrg JH7110_SYSRST_QSPI_APB>, <&syscrg JH7110_SYSRST_QSPI_AHB>, <&syscrg JH7110_SYSRST_QSPI_REF>; - reset-names = "rst_apb", "rst_ahb", "rst_ref"; + reset-names = "qspi", "qspi-ocp", "rstc_ref"; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; - #address-cells = <1>; - #size-cells = <0>; + cdns,trigger-address = <0x0>; + status = "disabled"; }; syscrg: clock-controller@13020000 {